Nanoelectronics (NANO)
Our main focus is to develop integrated circuits and systems by using state-of-the-art technology. The activity comprises both the computer-aided design process, real chip implementations in nanometer technology, testing and evaluation. Real application specific integrated circuits (ASICs) are made using analog, digital or mixed-mode technologies. The group is focusing on designing power efficient, robust nano circuits (“green electronics”). Typical applications are biomedical engineering and space technology. Major research activities are within wireless sensor networks and radio solutions, data conversion, low power/low voltage digital signal processing, neuromorphic electronics. The new emerging computing paradigm of numerous, tiny, self-contained, net-based sensor and actuator nodes interacting directly with the environment (“Smart Environment Technology”), is the computing technology of the future.
Reduced supply voltages, increased leakage currents and relatively slower wire interconnections compared to gate delays represent great design challenges. Next generation integrated RF technology is moving from microwave to millimeter wave frequencies challenging circuit and system design even more. Both down-scaling and high frequency performance (picosecond switching at picoampere current levels) are important future challenges in CMOS circuit design. Digging into this material will give rise to new opportunities and interesting solutions and implementation principles for future nano systems.
The research group has advanced, state-of-the-art design tools and several laboratories for circuit prototyping, measurement and testing, and we are currently in the process of expanding the laboratory facilities in the new Ole-Johan Dahl´s building by implementing PICOLab. PICOLab will consist of a Farady chamber for shielding at ultra low current levels (picoampere), an advanced prototyping lab and an anechoic chamber for millimeter and microwave measurements. The Nanoelectronics group is member of the common European university program Europractice for sharing design tools and semiconductor processing expenses. Currently, we are using 90nm and 65nm CMOS processes.