Mismatch calibration of a 1-bit time interleaved sampling architecture

Time interleaving of ADCs allows for conversion rates that are not feasible using a single channel ADC. However, mismatch among the channels impact parameters such as offset, timing, gain, and bandwidth, giving rise to undesirable artifacts in the sampled signal.

This master project will focus on trimming suitable for a 1-bit time interleaved sampling architecture for signals up to 10 GHz. Online or offline schemes for estimating the mismatch of interest (primarily amplitude offset and timing mismatch) should be considered. Further, mechanisms for trimming the mismatch should be evaluated. GHz signals impose stringent demands on parasitics, and the impact of the trimming scheme must be considered. A prototype of the 1-bit time interleaved sampling architecture with trimming should be implemented and measured to demonstrate the effectiveness of the proposed scheme.

Emneord: ADC, Electronics
Publisert 23. sep. 2017 12:03 - Sist endret 23. sep. 2017 12:03

Omfang (studiepoeng)