FPGA that emulates digital video output from CMOS image sensor

Design of FPGA that emulates digital video output from CMOS image sensor with programmable signal/noise ratio

Design FPGA based system that outputs digital video stream with programmable pixel count (VGA, HDTV, etc) and programmable video rate (e.g. 50Hz or 60Hz). The images will consist of ideal (noise free) baseline image with noise superimposed; thus emulating non-ideal behavior of CMOS image sensor. This can be used to analyse noise correction algorithms used in CMOS cameras. Noise algorithms can include white noise, 1/f noise, RTS noise, fixed pattern noise, etc.

Anbefalt faglig bakgrunn: INF3430, INF5430
, (INF5442)

 

Kontaktpersoner:


UiO: Jim Tørresen, 2285 2454, jimtoer@ifi.uio.no

Omnivision: Johannes Sølhusvik, johannes.solhusvik@ovt.com

 

Emneord: FPGA
Publisert 26. sep. 2016 13:08

Omfang (studiepoeng)

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