Yngvar Berg

• Azadmehr, Mehdi; Paprotny, Igor & Berg, Yngvar (2019). Q-Loading of Colpitts-Based Mass-Sensing Oscillators in Resonator-based MEMS Airborne Particulate Matter (PM) Sensors. IEEE International Symposium on Consumer Electronics.  ISSN 2158-3994. . doi: 10.1109/ICCE.2019.8662115
• Azadmehr, Mehdi; Schreyer-Miller, Aaron; Paprotny, Igor & Berg, Yngvar (2019). A New Differential Oscillator with T-type Feedback, In Satyajit Chakrabarti & Himadri Nath Saha (ed.),  2018 9th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON): 8th-10th November, 2018.  IEEE.  ISBN 978-1-5386-7693-6.  Electronics.  s 779 - 782 Show summary

  In this paper we present a new differential T-type feedback oscillator using digital inverters as the gain stage. The T-type feedback is a high-Q, high pass resonator formed by two capacitors and one inductor. The differential operation is achieved by connecting two single-ended oscillators through an inductor together. We present small signal model, analysis and simulation results of the oscillator realized using CMOS inverter and drive expression for its resonance frequency. Measurement results using discrete components are used to verify the operation of the circuit. The differential oscillator was also connected to a crystal with a frequency of 4.9152MHz and measurement results are provided.

• Marchetti, Luca; Azadmehr, Mehdi & Berg, Yngvar (2019). A Bidirectional Front-End for Discrete Resonating Transducers Based on A Non Ring Oscillator, In  16th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON).  IEEE conference proceedings.  ISBN 978-1-7281-3361-4.  19261241.  s 242 - 245
• Mirmotahari, Omid; Berg, Yngvar; Fremstad, Ester & Damsa, Crina I. (2019). Student engagement by employing student peer reviews with criteria-based assessment. IEEE Global Engineering Education Conference, EDUCON.  ISSN 2165-9559.  April-2019, s 1152- 1157 . doi: 10.1109/EDUCON.2019.8725174 Full text in Research Archive.
• Mirmotahari, Omid; Berg, Yngvar; Gjessing, Stein; Fremstad, Ester & Damsa, Crina I. (2019). A Case-Study of Automated Feedback Assessment. IEEE Global Engineering Education Conference, EDUCON.  ISSN 2165-9559.  April-2019, s 1190- 1197 . doi: 10.1109/EDUCON.2019.8725249 Full text in Research Archive.
• Azadmehr, Mehdi; Paprotny, Igor & Berg, Yngvar (2018). A Differential Complementary Colpitts Oscillator based on Common Drain Topology, In S. I. Ao; Craig Douglas & Warren S. Grundfest (ed.),  Proceedings of the World Congress on Engineering and Computer Science 2018. International Conference on Circuits and Systems (ICCS 18). 23-25 October, 2018, San Francisco, USA. Vol I.  Newswood Limited.  ISBN 978-988-14048-1-7.  Paper.  s 20 - 23
• Dadashi, Ali; Berg, Yngvar & Mirmotahari, Omid (2018). Energy-efficient, fast-settling, modified nested-current-mirror, single-stage-amplifier for high-resolution LCDs in 90-nm CMOS. Analog Integrated Circuits and Signal Processing.  ISSN 0925-1030.  97(2), s 253- 259 . doi: 10.1007/s10470-018-1220-7
• Dell’Anna, Francesco Giuseppe; Dong, Tao; Li, Ping; Wen, Yumei; Azadmehr, Mehdi; Casu, Mario R & Berg, Yngvar (2018). Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers. Sensors.  ISSN 1424-8220.  18(4) . doi: 10.3390/s18041245 Show summary

  This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs) powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE) for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs) for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal

• Dell’Anna, Francesco Giuseppe; Dong, Tao; Li, Ping; Wen, Yumei; Yang, Zhaochu; Casu, Mario R; Azadmehr, Mehdi & Berg, Yngvar (2018). State-of-the-Art Power Management Circuits for Piezoelectric Energy Harvesters. IEEE Circuits and Systems Magazine (CAS Magazine).  ISSN 1531-636X.  18(3), s 27- 48 . doi: 10.1109/MCAS.2018.2849262
• Dell’Anna, Francesco Giuseppe; Dong, Tao; Li, Ping; Yumei, Wen; Azadmehr, Mehdi & Berg, Yngvar (2018). Low-power voltage multiplier synthesis tool for preliminary topology identification, In  ICOSST 2017 International Conference on Open Source Systems and Technologies: Proceedings: 18-20 December, 2017 Lahore, Pakistan.  IEEE.  ISBN 9781538616581.  Paper.  s 24 - 29 Show summary

  This paper introduces a synthesis tool designed for low-power voltage multipliers. Voltage multipliers are rectifiers employed to generate a constant output voltage, which exceeds the peak-to-peak amplitude voltage of the input signal. At low power levels the attained performance of conventional voltage multipliers is strictly related to the transistor threshold voltage in the multiplication chain, which, at low voltage levels (tens of mV), are operated primarily in the subthreshold region or in cutoff mode. To improve the power conversion efficiency of voltage multipliers at low power levels, this paper introduces a novel passive threshold compensation technique to enhance the transistor conductivity, providing a static bias voltage at the gate of the transistors. Furthermore, a CAD oriented synthesis tool for the presented threshold compensation technique is proposed. The synthesis tool gives a preliminary indication on the rectifier topology (number of stages and compensation order) given target environmental conditions, target output performance, and adopted components in the rectification chain. The core algorithm is based trial and error simulator for the simplified rectifier model, which is employed to speed up the computations pertaining the voltage multiplier synthesis.

• Elgesem Schumacher, Ole Herman; Mirmotahari, Omid & Berg, Yngvar (2018). Ultra-Low-Voltage Dual-Rail NAND/NOR for High Speed Processing, In  The Eleventh International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS).  International Academy, Research and Industry Association (IARIA).  ISBN 978-1-61208-664-4.  Papers.  s 1 - 4
• Marchetti, Luca; Berg, Yngvar & Azadmehr, Mehdi (2018). A Compact Bidirectional Pseudo Floating Gate Front-End for Resonating Sensors based on NAND and NOR logic Gates, In  2018 IEEE International Conference on Semiconductor Electronics (ICSE2018): Proceedings: 15 – 17 August 2018 Pullman Kuala Lumpur City Centre Hotel & Residence, Kuala Lumpur, Malaysia.  IEEE.  ISBN 978-1-5386-5283-1.  Paper.  s 221 - 225 Show summary

  In this paper we present an alternative method to realize a compact bidirectional Front-End for resonating sensors based on Ring Down Method (RDM) and pseudo floating gate amplifier (PFGA). This goal is achieved by using the voltage buffer inside the PFGA for both biasing of the amplifier and actuation of the sensor. The proposed analog front-end doesn't require any coupling capacitor, minimizing the area occupied by the circuit. Simulations in AMS-350nm CMOS technology with a power supply of 3.3V and measurements on a prototype implemented with discrete components have been used to verify the correct operation of the system. The Front-end was realized by using the integrated circuits (ICs) CD4007UBE and ALD1103, and tested with a real piezoelectric transducer (MURATA MA40S4R), characterized by a resonant frequency of 40kHz. Measurement and simulation results show that the proposed circuit is a good candidate to realize a compact and bidirectional pseudo floating gate front-end, which resembles the circuit of NAND and NOR logic gates.

• Marchetti, Luca; Berg, Yngvar & Azadmehr, Mehdi (2018). A Discrete Implementation of a Semi-Floating Gate Amplifier for Resonating Sensor Front-End, In Andrzej Napieralski (ed.),  Proceedings of 25th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2018): Gdynia, Poland June 21-23, 2018.  IEEE.  ISBN 978-1-5386-5911-3.  Paper.  s 97 - 102 Show summary

  The growing need of electronic sensors and transducers in modern and portable applications requires to research new design methods, which aim to lower the power consumption and reduce the occupied area of the sensor interface circuitry. In this work we present the implementation of a semi-floating gate amplifier (SFGA) to realize a compact and low power resonating sensor front-end. The prototype has been fabricated by using the commercial integrated circuit CD4007UBE and tested with a power supply of 3.3V. Measurement results show that the main trade-off of this circuit is between gain and bandwidth. The maximum values recorded for these two parameters are: 150VN and 2MHz respectively. The circuit has been tested with an input sinusoidal signal and then connected to a Butterworth Van Dike (BvD) load. This type of load is commonly used to mimic the behavior of a real resonating transducer. The average current absorbed by the amplifier during the normal operation is 6μA leading to a static power consumption of 19.8μW . These values refer to a read-out frequency of 100Hz.

• Marchetti, Luca; Berg, Yngvar & Azadmehr, Mehdi (2018). A Low Power, High Gain Semi-Floating Gate Amplifier for Resonating Sensors Front-End. Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI.  ISSN 2159-3469.  2018, s 458- 463 . doi: 10.1109/ISVLSI.2018.00089 Show summary

  In this work, we propose a low power and high gain electronic Front-end for resonating sensors based on semi-floating-gate inverting amplifiers (SFGA). Low power and high gain are achieved using a novel biasing technique of the floating gates in SFGA. The proposed amplifier has been simulated in AMS-350nm CMOS technology, characterized by very low leakages. Gain, output swing and bandwidth can be controlled by applying a proper biasing voltage. Simulation results show a trade-off between gain and bandwidth. However, the best performance recorded are: gain of 54dB (505 V/V) and bandwidth of 1.63GHz. A transient analysis with a sinusoidal input has been performed in order to verify the working principle of the SFGA. The implemented circuit provides a static power consumption of 69μW with a power supply of 3.3V. At the end of this work, the SFGA has been connected as a sensor front-end to read-out the response of a resonating sensor, which has been modelled with a Butterworth Van Dike model of a real device (MURATA MA40S4R).

• Marchetti, Luca; Berg, Yngvar & Azadmehr, Mehdi (2018). A Self-Actuated Front-End for Resonating Sensors, In  TENCON 2018 - 2018 IEEE Region 10 Conference.  IEEE conference proceedings.  ISBN 978-1-5386-5457-6.  kapittel.  s 559 - 564 Show summary

  In this work, we propose a novel self-actuated analog front-end (AFE) for resonating sensors, realized in pseudo floating gate technology. The core of the analog front-end is based on a re-configurable circuit, which works as a SRAM cell when the resonating sensor must be actuated and behaves as a pseudo floating gate amplifier (PFGA) when the sensor response must be read-out. The timing for the actuation/readout cycle is provided by an inverter based control system, which is connected with the AFE in a positive feedback loop. The use of solely inverter logic gates to implement the whole system simplifies the design of the circuit, minimizes the occupied area, and makes possible to use the proposed system in low voltage applications (V DD < 3.3V). The operation of the proposed circuit has been verified by simulations in AMS-350nm CMOS technology with a power supply of 3.3V. At the end of this paper, the effects of process, temperature and power supply (PVT) variations have been investigated, and a few solutions to compensate these side effects have been proposed. Finally, the average power consumption of the circuit has been measured to be 445µW, which is in the same order of other front-ends described in literature.

• Marchetti, Luca; Berg, Yngvar & Azadmehr, Mehdi (2018). A bidirectional front-end for ultrasonic pulse-echo measurements, In  2018 IEEE 15th International Conference on Networking, Sensing and Control (ICNSC). March 27-29, Zhuhai, China.  IEEE.  ISBN 978-1-5386-5053-0.  Paper.
• Marchetti, Luca; Berg, Yngvar & Azadmehr, Mehdi (2018). A self-cascode pseudo floating gate front-end for resonating sensors, In  2018 International ECTI Northern Section Conference on Electrical, Electronics, Computer and Telecommunications Engineering (ECTI-NCON 2018): Chiang Rai, Thailand 25 – 28 February 2018.  IEEE.  ISBN 978-1-5386-3553-7.  Chapter.  s 89 - 94 Show summary

  In this work, we have demonstrated an alternative design strategy based on self-cascode transistors to improve the gain and the power consumption of a pseudo floating gate amplifier (PFGA), with the minimum area occupation. This is accomplished by implementing the inverter in the PFGA using self-cascode transistors, which provides all the advantages of a cascode amplifier (higher gain and lower power consumption), with a negligible overhead in terms of area occupation. The performance of a self-cascode pseudo floating gate amplifier (SC-PFGA) are comparable to those ones of a current-starved pseudo floating gate amplifier (CS-PFGA), with the difference that CS-PFGA requires also the circuitry to generate two reference voltages. For this reason the SC-PFGA is more compact and less power consuming than a CS-PFGA. On the other hand, the SC-PFGA doesn't provide the possibility to tune the bandwidth or the gain of the amplifier, which can be negligible in applications in which this feature is not necessary. In this work, we have compared the performance between PFGA and SC-PFGA by designing and simulating these circuits in AMS-350nm CMOS process with a power supply of 5V. This specific implementation can be applied in all those systems in which low leakage currents or voltages higher than 5V are required. In order to prove the effectiveness of this technique, the amplifier has been tested as analog front-end of a generic resonating sensor approximated with a Butterworth Van Dike model. Simulation results show that the self cascode amplifier provides a gain 7 times greater and a power consumption 12 times smaller than the ones provided by the PFGA.

• Mirmotahari, Omid & Berg, Yngvar (2018). Structured peer review using a custom assessment program for electrical engineering students. IEEE Global Engineering Education Conference, EDUCON.  ISSN 2165-9559.  2018-April, s 999- 1006 . doi: 10.1109/EDUCON.2018.8363339
• Mirmotahari, Omid; Berg, Yngvar & Damsa, Crina I. (2018). Innovating Assessment Practices Using Automated Feedback in Software in Computer Science Education. CEUR Workshop Proceedings.  ISSN 1613-0073.  2128 Full text in Research Archive.
• Mirmotahari, Omid; Berg, Yngvar; Langmyhr, Dag; Fremstad, Ester & Damsa, Crina I. (2018). Studentaktivisering gjennom bruk av hverandrevurdering for førstesemesters studenter i Canvas LMS: en forsøksstudie.. NIKT: Norsk IKT-konferanse for forskning og utdanning.  ISSN 1892-0713.  1(1) . doi: http://ojs.bibsys.no/index.php/NIK/article/view/521 Full text in Research Archive.
• Mirmotahari, Omid; Damsa, Crina I. & Berg, Yngvar (2018). Formative Feedback for Learning. Case Studies of Automated Feedback in Undergraduate Computer Science Education. Proceedings (International Conference of the Learning Sciences).  ISSN 1814-9316.  3, s 1577- 1578 Full text in Research Archive.
• Azadmehr, Mehdi; Marchetti, Luca & Berg, Yngvar (2017). A low power analog voltage similarity circuit. IEEE International Symposium on Circuits and Systems proceedings.  ISSN 0271-4302. . doi: 10.1109/ISCAS.2017.8050950 Show summary

  In this paper, we present a low power bump circuit for finding similarity between two voltages. The circuit is based on a voltage correlator that in combination with a differential pair achieves the low power behavior. The circuit has low power consumption and low sensitivity when the different between the two input is large, but as they approach each other the sensitivity increases. The proposed circuit is very simple in design and can have more than 4 orders of magnitude less power consumption than the normal bump circuit.

• Azadmehr, Mehdi; Marchetti, Luca; Elkharashi, Moataz & Berg, Yngvar (2017). A virtual Wheatstone bridge front-end for resistive sensors, In Giancarlo Fortino (ed.),  Proceedings of the 2017 IEEE 14th International Conference on Networking, Sensing and Control (ICNSC 2017) May 16-18, 2017, Calabria, Italy.  IEEE.  ISBN 978-1-5090-4428-3.  Paper. Show summary

  In this paper we present a novel front-end for resistive sensors based on a simple resistive voltage divider. This front-end utilizes a sampling technique to mimic the Wheatstone bridge in functionality, offers high precision and is fast at the same time more power conservative compared to the traditional Wheatstone bridge.

• Marchetti, Luca; Berg, Yngvar & Azadmehr, Mehdi (2017). A bidirectional front-end with bandwidth control for actuation and read-out of MEMS resonating sensors, In . IEEE (ed.),  2017 MIXDES - 24th International Conference Mixed Design of Integrated Circuits and Systems: Bydgoszcz, Poland 22-24 June 2017.  IEEE.  ISBN 978-1-5090-6486-1.  Conference paper.  s 185 - 188 Show summary

  In this paper we propose a bidirectional front-end for resonating sensors with bandwidth control used to remove the high order oscillating modes. The electronic interface is based on an inverter working as amplifier biased by a voltage buffer, both realized in CMOS technology. The bandwidth of the amplifier can be tuned by varying a bias voltage which controls the high cut-off frequency of the front-end. A prototype was realized and tested with discrete components on a PCB. The tests were performed by using a RLC load which can be proved to be a good approximated model for a resonating sensor. The values for the load are R = 100Ω, L = 10mH, C = 270pF. Measurements were taken for Vdd=5V, Vdd=10V, Vdd=15V. Measurement results show that the bias voltage VHF affects both DC and AC characteristics of the amplifier, in particular the bandwidth varies in a range between a few kHz to a maximum of 5 MHz. A high order mode oscillation has been simulated by adding a sine wave generator at 2 MHz in series to the RLC load which was removed by filtering action of the amplifier.

• Marchetti, Luca; Berg, Yngvar & Azadmehr, Mehdi (2017). An Autozeroing Inverter Based Front-End for Resonating Sensors, In . IEEE (ed.),  2017 12th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).  IEEE.  ISBN 978-1-5090-6377-2.  Conference paper. Show summary

  In this paper we propose a new front-end for resonating sensors which is based on a logic inverter working as amplifier. The front-end is compact and auto-zeroing which makes it a good candidate for integration and for low power applications. It has been simulated in AMS-350nm CMOS Technology and a prototype has been fabricated using discrete components on a PCB. The circuit was tested with a BvD load implemented in discrete components, which can be proved to be a good model for a resonant sensor. The components used to implement the BvD load are: Lm = 3mH, Rb = 200Ω, Cs = 560pF, Ce = 3.3nF which leads to a resonant frequency of 140 KHz. The bandwidth of the amplifier is 380kHz and the mid-band gain is 55V/V. The prototype has been tested with a power supply of 5V.

• Marchetti, Luca; Berg, Yngvar & Azadmehr, Mehdi (2017). Analysis of the effect of channel leakage on design, characterization and modelling of a high voltage pseudo-floating gate sensor-front-end. Electronics.  ISSN 2079-9292.  6(4), s 1- 26 . doi: 10.3390/electronics6040079 Full text in Research Archive. Show summary

  In this paper, we analyze the effects of channel leakage on the design, modelling and characterization of a high voltage pseudo-floating gate amplifier (PFGA) used as sensor front-end. Leakages are known as a major challenge in new modern CMOS technologies, which are used to bias the PFGA, and consequently affect the behavior of the amplifier. As high voltages are desired for actuation of many types of resonating sensors, especially in ultrasound applications, PFGA implemented in high voltage and low leakage technologies, such as older CMOS fabrication processes or power MOSFET can be the only option. The challenge with these technologies used to implement the PFGA is that the leakages are very low, which affect the biasing of the floating gate. However, the numerous advantages of this type of amplifier, implemented with modern fabrication processes, such as high flexibility, compactness, low power consumption , etc. encouraged the authors to research about this topic. This work provides analysis of the working principle and the design rules for this amplifier, emphasizing the major differences between PFGA implemented in low leakage and high leakage technologies. Static and dynamic analysis, input offset and non-linearity of the PFGA are the main topics of this article. Three different design approaches are presented in this paper, in order to provide a more general design procedure and offset compensation for any low leakage PFGA. The amplifier has been simulated in AMS-0.35mm CMOS models for supply voltages of 5 V and 10 V. Two prototypes have been realized to verify the validity of the modelling and the simulation results. Both devices have been realized by using discrete components and mounted on a printed circuit board. In this work, MOSFETs are realized by using commercial IC CD4007UB and 2N7000. Measurement results of the first prototype proved that the implementation of a low leakage PFGA is possible after that the input offset of the amplifier has been compensated. Measurement results of the second prototype have been used to characterize the low leakage PFGA, extracting the best performances from this amplifier, realized with less components and providing a more compact device. Finally, design rules have been summarized in order to implement this amplifier, which enjoys compactness and a relative low power dissipation.

• Marchetti, Luca; Berg, Yngvar & Azadmehr, Mehdi (2017). Design and modelling of a bidirectional front-end for resonating sensors based on pseudo floating gate amplifier. Electronics.  ISSN 2079-9292.  6(3) . doi: 10.3390/electronics6030068 Full text in Research Archive. Show summary

  In this paper, we characterize and model a bidirectional front-end based on pseudo-floating gate amplifier (PFGA) for actuation and read-out of resonating sensors. The basic idea consists of swapping the power supply of the PFGA in order to change the directionality of the front-end. A detailed description of the system has been discussed in this paper and supported by simulations and measurement results. A prototype has been fabricated using discrete components and tested with a real transducer (Murata MA40S4) and a Butterworth Van Dyke (BvD) load, which has proved to be proved to be a well approximated model for resonant sensors. The bidirectional amplifier has been implemented with the integrated circuit CD4007UB, which is a commercial discrete component containing low leakage MOSFET. The values chosen for the BvD load are Rb = 330 W, Lm = 60 mH, Cs = 450 pF, CE = 2.2 nF, which are approximately the same values of the lumped parameters reported in the data-sheet of the real sensor. This transducer is characterized by a nominal resonant frequency of 40 kHz. Measurement results show good fitting with the models developed in this work and the possibility to predict the sensor response by using the BvD load.

• Marchetti, Luca; Berg, Yngvar; Mirmotahari, Omid & Azadmehr, Mehdi (2017). A control system for a low power bidirectional front-end for resonating sensors, In Giancarlo Fortino (ed.),  Proceedings of the 2017 IEEE 14th International Conference on Networking, Sensing and Control (ICNSC 2017) May 16-18, 2017, Calabria, Italy.  IEEE.  ISBN 978-1-5090-4428-3.  55.  s 322 - 326 Show summary

  In this paper, we propose a digital control system to automatize the operation of a bidirectional front-end for resonating sensors. Due to the simplicity, the control system is power conservative and compact. The main source of power consumption in the bidirectional front-end is the amplifier used to read-out the sensor. Power can be saved by turning off the amplifier after a few periods of the oscillating signal, which is enough to detect the resonant frequency of the sensor. The concept was initially proved by performing simulations in SPICE by using AMS-350nm CMOS technology model. A prototype was realized with discrete components on a PCB and tested with a power supply of 5V. The reading cycle was fixed at 10kHz and a RLC load has been used as model of a MEMS resonant sensor. The values for the RLC components used for the tests are 100Ω, 270pF, 10mH. The nominal power consumption of the front-end without the support of the sleeping mode is 1.7mW while the sleeping mode with reading one oscillation period reduces the power dissipation to 270μW(15.88% of 1.7mW).

• Mirmotahari, Omid & Berg, Yngvar (2017). Erfaringer fra strukturert peer review ved bruk av et egetutviklet sensureringsprogram. NIKT: Norsk IKT-konferanse for forskning og utdanning.  ISSN 1892-0713.  1(1)
• Mirmotahari, Omid & Berg, Yngvar (2017). High-Speed Digital Domino Logic for Ultra-Low Supply Voltages. Circuits, systems, and signal processing.  ISSN 0278-081X.  36(12), s 4774- 4788 . doi: 10.1007/s00034-017-0632-4
• Mirmotahari, Omid & Berg, Yngvar (2017). Individuell «automagisk» tilbakemelding på skriftlig eksamen. Nordic Journal of STEM Education.  ISSN 2535-4574.  1(1), s 287- 293 . doi: 10.5324/njsteme.v1i1.2327 Full text in Research Archive.
• Dadashi, Ali; Mirmotahari, Omid & Berg, Yngvar (2016). A New Fully Differential Adaptive CMOS Line Driver Using Fuzzy Controller Suitable for ADSL Modems. Circuits and Systems.  ISSN 2153-1285.  7(8), s 1307- 1323 . doi: 10.4236/cs.2016.78114 Full text in Research Archive.
• Dadashi, Ali; Mirmotahari, Omid & Berg, Yngvar (2016). NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates. Circuits and Systems.  ISSN 2153-1285.  7(8), s 1916- 1926 . doi: 10.4236/cs.2016.78166
• Marchetti, Luca; Berg, Yngvar; Mirmotahari, Omid & Azadmehr, Mehdi (2016). Bidirectional Front-End for Piezoelectric Resonator, In  2016 IEEE 13th International Conference on Networking, Sensing, and Control (ICNSC 2016).  IEEE conference proceedings.  ISBN 978-1-4673-9975-3.  Chapter. Show summary

  This paper presents a bidirectional circuit as front-end for piezoelectric ceramic resonators. The front-end both actives and reads the response of the resonator in different directions and the directionality of the front-end is controlled by swapping the supply rails. Experimental results are obtained by measuring on a semi-discrete board prototype. The resonant frequency of the sensor is 110kHz, the bandwidth of the bidirectional front-end is 1kHz - 500kHz which was implemented by using a CD4007UBE IC. Results show that the system provides an easy and effective way to send an activation signal and to read the response of a piezoelectric resonator.

• Marchetti, Luca; Romi, Amar; Berg, Yngvar; Mirmotahari, Omid & Azadmehr, Mehdi (2016). A discrete implementation of a bidirectional circuit for actuation and read-out of resonating sensors, In Alberto Bosio (ed.),  2016 11th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS).  IEEE conference proceedings.  ISBN 978-1-5090-0336-5.  Chapter. Show summary

  In this paper we propose a simple and compact way to realize a bi-directional interface to drive resonant sensors. The bi-directional interface can be set to both activate the resonating sensor (activation mode) and to read its response (read-out mode). During the normal operation of the system these two modes are activated alternatively, depend on the state of the control signals. The directionality of this device is decided by swapping the power supply rails. The system has been tested using a RLC load, considered as the model for a resonant sensor. Experimental results of a discrete board prototype show the applicability of the interface for resonant load.

• Mirmotahari, Omid & Berg, Yngvar (2016). Ultra Low-Voltage Static Precharge NAND/NOR Gates, In Geok Ing (ed.),  Proceedings of the 2014 IEEE 5th International Nanoelectronics Conference (INEC).  IEEE conference proceedings.  ISBN 978-1-4673-4841-6.  Nanoelectronics.
• Mirmotahari, Omid; Dadashi, Ali; Azadmehr, Mehdi & Berg, Yngvar (2016). High-speed dynamic dual-rail ultra low voltage static CMOS logic operating at 300 mV, In Alberto Bosio (ed.),  2016 11th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS).  IEEE conference proceedings.  ISBN 978-1-5090-0336-5.  Chapter. Show summary

  In this paper we propose a differential dynamic dual rail CMOS logic style for ultra-low-voltage and high-speed operation. For a supply voltage equal to 300mV using a 90nm TSMC CMOS process the speed of the proposed logic style is more than 25 times faster than traditional dual rail clocked voltage switch logic CVSL

• Azadmehr, Mehdi; Khajeh, Belal & Berg, Yngvar (2015). A New self-sensing approach for actuation and readout of Piezoelectric resonating sensor, In Chi-Hsu Wang & Yo-Ping Huang (ed.),  ICNSC15, 12th IEEE international Conference on Networking, Sensing and Control.  IEEE conference proceedings.  ISBN 978-1-4673-6900-8.  Sensors.  s 232 - 235 Show summary

  In this paper we proposed a new approach to actuate and readout of resonating piezoelectric sensors to realize concept of self-sensing. In the circuit three transistors are used to differentiate between actuation and readout modes. We evaluated a given piezoelectric resonating sensor and the proposed Circuit analytically and with simulations. We also evaluated the applicability of our circuit for mass detection purposes and showed that piezoelectric resonant sensor with our proposed circuit can be a good candidate for mass detection in picogram range.

• Berg, Yngvar & Mirmotahari, Omid (2015). Flexible Ultra-Low-Voltage CMOS Circuit Design Applicable for Digital and Analog Circuits Operating below 300mV, In Lisa O'Conner (ed.),  2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).  IEEE Press.  ISBN 978-1-4799-8718-4.  Session 33.  s 646 - 651 Show summary

  A generic ultra low-voltage (ULV) CMOS design approach is presented. By applying a floating capacitor to the gate terminal of the enhanced driving transistors, obtained by using a charge injection technique, we may change the ON and OFF currents. The delay in circuits where the enhanced transistors are utilized can be reduced significantly compared to complementary CMOS. The current level of the transistors may be increased for high speed and decreased for low power applications. The design approach may be used to implement ultra low-voltage and high-speed digital logic and Flip-Flops. In addition, the generic technique can be used to implement multiple-valued and analog ultra low-voltage CMOS circuits. For ultra low-voltage digital applications the delay may be reduced to less than 10% compared to static CMOS. The high speed Flip-FLOP presented shows a similar increase in speed compared to conventional Flip-Flops for low supply voltages. For the analog circuit presented the increased current level is used to obtain rail-to-rail operation at higher frequencies than conventional analog circuits.

• Berg, Yngvar & Mirmotahari, Omid (2015). Low-voltage and high-speed CMOS circuit design with low-power mode, In Mohamad Abbas; M. Chrzanowska-Jesk & Watheq El-Kharashi (ed.),  2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS).  IEEE conference proceedings.  ISBN 978-1-5090-0246-7.  Kapittel.  s 57 - 60 Show summary

  In this paper we present a modified ultra-lowvoltage and high-speed domino logic style with sleep mode for low-power and low-energy applications. The performance compared to conventional clock voltage switch logic is 15 times higher in terms of speed for a supply voltage equal to 300mV The low-power sleep mode consumes less than 1% of the power in high-performance mode. The CMOS process used for the simulated data presented is 90nm TSMC.

• Dadashi, Ali; Berg, Yngvar & Mirmotahari, Omid (2015). High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inveter, In Lisa O'Conner (ed.),  2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).  IEEE Press.  ISBN 978-1-4799-8718-4.  Session 05.  s 86 - 90
• Dadashi, Ali; Mirmotahari, Omid & Berg, Yngvar (2015). An ultra-low-voltage, semi-floating-gate, domino, dual-rail, NOR gate, In Mohamad Abbas; M. Chrzanowska-Jesk & Watheq El-Kharashi (ed.),  2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS).  IEEE conference proceedings.  ISBN 978-1-5090-0246-7.  Kapittel.  s 61 - 64
• Mirmotahari, Omid & Berg, Yngvar (2015). Reliability of High Speed Ultra Low Voltage Differential CMOS Logic. Circuits and Systems.  ISSN 2153-1285.  6(5), s 121- 135 . doi: 10.4236/cs.2015.65013 Full text in Research Archive. Show summary

  In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.

• Mirmotahari, Omid; Dadashi, Ali; Azadmehr, Mehdi & Berg, Yngvar (2015). Novel high-speed dynamic differential ultra low voltage logic for supply-voltage below 300 mV, In Mohamad Abbas; M. Chrzanowska-Jesk & Watheq El-Kharashi (ed.),  2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS).  IEEE conference proceedings.  ISBN 978-1-5090-0246-7.  Kapittel.  s 53 - 56 Show summary

  In this paper we propose a differential dynamic dual rail CMOS logic style for ultra-low-voltage and high-speed operation. For a supply voltage equal to 300mV using a 90nm TSMC CMOS process the delay of the proposed logic style is reduced more than 96% compared to the delay of dual rail clocked voltage switch logic.

• Azadmehr, Mehdi; Khakpour Khajeh, Belal & Berg, Yngvar (2014). A bidirectional circuit for actuation and read-out of resonating sensors, In  2014 IEEE Faible Tension Faible Consommation (FTFC).  IEEE conference proceedings.  ISBN 978-1-4799-3773-8.  Paper. Show summary

  In this paper we have demonstrated a novel approach for actuation and read-out of resonating sensors. In this approach, instead of reading the amplitude of the resonating beam in resonance, we use the frequency of the beam as a measure of the sensors response. By using a bidirectional amplifier a pulse is sent to a resonating sensor in one direction and the frequency response of the sensor is measured using the opposite direction of the amplifier. This approach results in more compact and more power conservative systems. This approach mimics the way radars operate where a pulse is sent out and the reflection is measured. The circuit is very compact with low component spread and consumes an average power of 22μW and a maximum power of 100μW when actuating the sensor.

• Azadmehr, Mehdi; Khakpour Khajeh, Belal & Berg, Yngvar (2014). An ultra-low voltage tunable dual-Band Pass Filter, In  Multi-Conference on Systems, Signals & Devices (SSD), 2014 11th International.  IEEE conference proceedings.  ISBN 978-1-4799-3866-7.  Paper. Show summary

  In this paper we present an ultra-low voltage dual Band Pass Filter with tunable pass bands. The dual band pass filter has two pass bands which can be tuned individually and can operate at supply voltages down to 300mV. The filter is based on Pseudo Floating-Gate and in addition to frequency band adjustment, it offers gain. Both the center frequencies are controlled electronically using bias voltages through the bulk of transistors. The filter benefits from low component spread and compactness, containing only small size transistors and capacitors suited for integration. The simulations presented in this paper are valid for the 90nm CMOS transistor models from STM having a VDD equal to 1.2V and threshold voltage of 250mV.

• Mirmotahari, Omid & Berg, Yngvar (2014). Latching Scheme in Multiple-Valued Recharged Logic. International Journal of Engineering ,Science and Innovative Technology.  ISSN 2319-5967.  3(3), s 57- 72
• Azadmehr, Mehdi & Berg, Yngvar (2013). A Bulk-controlled Pseudo-Floating Gate Bandpass Filter. Recent Advances in Electrical Engineering.  ISSN 1790-5117.  CSCS 13 / ELEL 13, s 59- 63 . doi: 10.1109/norchp.2008.4738294 Show summary

  In this paper we present a bulk-controlled Pseudo Floating-Gate (BCPFG) Bandpass filter. The filter has a limited Open-Loop gain and linearity for supply voltages down to 600mV . The filter is based on Pseudo Floating-Gate active load amplifier and in addition to gain, it offers frequency band adjustment. Both the low- and high-frequency cutoffs are controlled electronically using bias voltages through the transistor bulks. The BCPFG BP filter enjoys low component spread and compactness, containing only small size transistors and capacitors suited for integration. The simulations presented in this paper are valid for the 90nm CMOS transistor models from STM having a V DD equal to 1.2V and threshold voltage of 250mV.

• Berg, Yngvar (2013). High Speed and Ultra Low-Voltage CMOS Carry Propagation Chain using Floating-Gate Transistors, In V. Privman (ed.),  Sixth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS 2013).  International Academy, Research and Industry Association (IARIA).  ISBN 978-1-61208-302-5.  Session 1: Elektronics.  s 1 - 6
• Mahmood, Sohail Musa & Berg, Yngvar (2013). High Speed and Ultra Low-voltage CMOS Domino Carry gates, In Agoujil Said; Collin Howe Hing Tang & Sorinel Oprisan (ed.),  RECENT ADVANCES in CIRCUITS, COMMUNICATIONS and SIGNAL PROCESSING.  World Scientific and Engineering Academy and Society.  ISBN 978-1-61804-164-7.  paper.  s 52 - 57
• Mahmood, Sohail Musa & Berg, Yngvar (2013). Static NP domino Carry gates for Ultra Low Voltage and High Speed Full Adders. North atlantic university union: International Journal of Circuits, Systems and Signal Processing.  ISSN 1998-4464.  7, s 199- 205
• Mahmood, Sohail Musa & Berg, Yngvar (2013). Ultra-low voltage and high speed NP domino carry propagation chain, In  2013 IEEE Faible Tension Faible Consommation (FTFC).  IEEE conference proceedings.  ISBN 978-1-4673-6105-7.  Session 3.
• Mirmotahari, Omid & Berg, Yngvar (2013). Robust Low-Power CMOS Precharge Logic, In  2013 IEEE Faible Tension Faible Consommation (FTFC).  IEEE conference proceedings.  ISBN 978-1-4673-6105-7.  session 1.  s 11
• Mirmotahari, Omid & Berg, Yngvar (2013). Robustness of the Ultra Low-Voltage Domino Gates CMOS, In V. Privman (ed.),  Sixth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS 2013).  International Academy, Research and Industry Association (IARIA).  ISBN 978-1-61208-302-5.  Session 1: Electronics.  s 7 - 12
• Azadmehr, Mehdi & Berg, Yngvar (2012). A band-tunable auto-zeroing amplifier. Recent Advances in Electrical Engineering.  ISSN 1790-5117.  3(CSCS 12), s 24- 28 Show summary

  In this paper we present a tunable Auto-Zeroing Amplifier(AZA). The amplifier is based on Pseudo Floating gate and in addition to gain, it offers frequency band adjustment. Both the low- and high-frequency cutoffs are controlled electronically using bias voltages, thus the amplifier can be used in design of various time continues filters. The peak gain of the AZA is 22dB dB at 100 MHz and has a bandwidth from. The AZA enjoys low component spread and compactness, containing only small size transistors and capacitors suited for integration. We will also show a second order section realized using the AZA. The simulations presented in this paper are valid for the 90nm CMOS transistor models from STM having a V DD equal to 1.2V and threshold voltage of 0.25V.

• Azadmehr, Mehdi & Berg, Yngvar (2012). An ultra-low voltage pseudo-floating gate amplifier, In  2012 Faible Tension Faible Consommation (FTFC).  IEEE conference proceedings.  ISBN 978-1-4673-0820-5.  Paper. Show summary

  In this paper we present an Ultra-Low Voltage Pseudo Floating-Gate Amplifier (ULVPFGA). The amplifier has high gain and high linearity for supply voltages down to 300mV. The amplifier is based on Pseudo Floating-Gate and in addition to gain, it offers frequency band adjustment. Both the low- and highfrequency cutoffs are controlled electronically using bias voltages through their bulk. The ULVPFGA enjoys low component spread and compactness, containing only small size transistors and capacitors suited for integration. We also show a second order section realized using the ULVPFGA. The simulations presented in this paper are valid for the 90nm CMOS transistor models from STM having a VDD equal to 1.2V and threshold voltage of 250mV.

• Berg, Yngvar (2012). A novel high speed differential ultra low-voltage CMOS Flip-Flop for high speed applications, In  CENICS 2012: The Fifth International Conference on Advances in Circuits, Electronics and Microelectronics.  International Academy, Research and Industry Association (IARIA).  ISBN 978-1-61208-213-4.  Chapter.  s 11 - 16 Show summary

  In this paper we present a simple ultra low-voltage and high speed D flip-flop. The Flip-Flop may be used in any standard digital low-voltage CMOS applications. Furthermore, the ultra low-voltage Flip-Flop offers reduced data to output delay compared to conventional CMOS Flip-Flops. Different master latch configurations are presented and a differential symmetric ultra low-voltage Flip-Flop is presented. Simulated data using HSpice and process parameters for 90nm CMOS are provided. Preliminary results show that the proposed Flip- Flop has a delay less than 20% compared to a conventional CMOS Flip-Flop.

• Berg, Yngvar (2012). Ultra Low-Voltage Differential Static D Flip-Flop for High Speed Digital Applications. North atlantic university union: International Journal of Circuits, Systems and Signal Processing.  ISSN 1998-4464.  6(4), s 263- 268 Show summary

  In this paper we present an ultra low-voltage and high speed D flip-flop. The flip-flop has an increased current level compared to standard CMOS circuits operating at low supply voltages. The increased current level is obtained by using a synchronized capacitive coupling to a semi floating-gate. The delay of the static differential flip-flop presented is less than 12% compared to conventional differential CMOS flip-flops. The presented circuits have been simulated using Hspice and are valid for 90nm TSMC CMOS process. The proposed high-speed and ultra low-voltage flip-flop can be used for any digital lowvoltage CMOS application.

• Berg, Yngvar (2012). Ultra low-voltage CMOS transconductance amplifiers. Analog Integrated Circuits and Signal Processing.  ISSN 0925-1030.  73(3), s 683- 692 . doi: 10.1007/s10470-012-9924-6 Show summary

  Simple and symmetrical ultra low-voltage current mode analog circuits and autozeroing amplifiers are presented. The low-voltage analog circuits are based on low-voltage inverters resembling precharge digital logic. Ultra low-voltage analog circuits can be operated at supply voltages down to 250 mV with rail-to-rail input and output swing. The output current of the ultra low-voltage symmetrical transconductance amplifier can be quite large due to a current boost technique. Ultra low-voltage analog circuits can be operated at supply voltages down to 250 mV with rail- to-rail input and output swing. The current headroom is 3 lA and the supply voltage is 300 mV. For supply voltages down to 300 mV simulated data shows that the maximum clock frequency is approximately 600 MHz.

• Berg, Yngvar & Azadmehr, Mehdi (2012). Novel linear autozeroing floating-gate amplifier for ultra low-voltage applications. International Journal of Social, Behavioral, Educational, Economic, Business and Industrial Engineering.  ISSN 2010-376X.  68, s 262- 265
• Berg, Yngvar & Azadmehr, Mehdi (2012). Novel ultra low-voltage and high-speed CMOS pass transistor logic, In  2012 Faible Tension Faible Consommation (FTFC).  IEEE conference proceedings.  ISBN 978-1-4673-0820-5.  Paper. Show summary

  In this paper we present a novel CMOS pass transistor logic style for ultra low-voltage and high speed digital applications. The circuits presented offer more than 90% delay reduction compared to conventional CMOS for supply voltages less than 400mV. Differential AND and NAND pass transistor gates presented and compared to complementary pass transistor logic CPL. Simulated data obtained by the Hspice simulation and relevant for 90nm TSMC process are provided.

• Berg, Yngvar & Azadmehr, Mehdi (2012). Symmetric Autozeroing Floating-Gate Current Mirror, Differential Pair and Transconductance Amplifier for Ultra Low-Voltage Applications. North atlantic university union: International Journal of Circuits, Systems and Signal Processing.  ISSN 1998-4464.  6(4), s 255- 262 Show summary

  In this paper we explore the symmetric autozeroing ultra low-voltage current mirror, differential pair and transconductance amplifier and present some applications. The ultralow transconductance amplifier has a current boost function and resembles switch-cap and auto-zero circuits. The current boost technique have been used to implement ultra-low voltage digital logic. The simulated data presented is relevant for a 90nm TSMC CMOS process.

• Berg, Yngvar & Mirmotahari, Omid (2012). High Speed and Ultra Low-voltage CMOS NAND and NOR domino gates. International Journal of Social, Behavioral, Educational, Economic, Business and Industrial Engineering.  ISSN 2010-376X.  68, s 258- 261 Show summary

  In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.

• Berg, Yngvar & Mirmotahari, Omid (2012). Novel Static Ultra Low-Voltage and High Speed CMOS Boolean Gates. North atlantic university union: International Journal of Circuits, Systems and Signal Processing.  ISSN 1998-4464.  6(4), s 249- 254 Show summary

  In this paper we present robust and high performance static ultra low-voltage CMOS binary logic. The delay of the ultra low-voltage logic presented are less than 10% of the delay of standard CMOS inverters. The logic gates presented are designed using semi floating-gate transistors and a current boost technique. The boolean gates resemble domino CMOS. The performance and robustness of different logic gates are examined and compared to complementary and domino CMOS logic.

• Berg, Yngvar & Mirmotahari, Omid (2012). Novel high-speed and ultra-low-voltage CMOS NAND and NOR domino gates, In  CENICS 2012: The Fifth International Conference on Advances in Circuits, Electronics and Microelectronics.  International Academy, Research and Industry Association (IARIA).  ISBN 978-1-61208-213-4.  Chapter.  s 5 - 10 Show summary

  In this paper we present novel ultra-low-voltage and high-speed CMOS NAND and NOR gates. For supply voltages below 500mV the delay for an ultra-low-voltage NAND2 gate is approximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch are much lesser than for conventional CMOS. Differential domino gates for AND2/NAND2 and OR2/NOR2 operation are presented. Ultra-low-voltage pass transistors are presented which can be used as latching gates. The ultra-low-voltage gates presented are going to be used for implementation oflow-voltage and high speed adders.

• Berg, Yngvar & Mirmotahari, Omid (2012). Static Differential Ultra Low-Voltage Domino CMOS logic for High Speed Applications. North atlantic university union: International Journal of Circuits, Systems and Signal Processing.  ISSN 1998-4464.  6(4), s 269- 274 Show summary

  In this paper we present a novel static differential ultra low-voltage (ULV) CMOS logic style for High-Speed applications . The proposed logic style is aimed for high speed serial adders in ultra low-voltage applications. The differential ultra low-voltage inverter presented have less than 10% of the delay than standard CMOS inverters for supply voltages less than 500mV . The simulated data presented is obtained using Hspice simulator and applying a 90nm TSMC CMOS process.

• Berg, Yngvar & Mirmotahari, Omid (2012). Ultra low-voltage and high speed dynamic and static CMOS precharge logic, In  2012 Faible Tension Faible Consommation (FTFC).  IEEE conference proceedings.  ISBN 978-1-4673-0820-5.  Paper. Show summary

  In this paper we present novel high speed and ultra low voltage domino invererters. The delay of the inverters are less than 4% of the delay for a standard CMOS inverter. A low power inverter is included and the simulated data for supply voltages in the range of 200mV to 400mV are provoded. Monte carlo simulation show that the ULV logic styles are less influenced by process mismatches than standard CMOS logic. Simulated data presented is obtained by HSpice and process parameters for the 90nm TSMC process.

• Mirmotahari, Omid; Berg, Yngvar & Høvin, Mats Erling (2012). Automation of Packing Cell in Fresh Fish Facilities. International Journal of Social, Behavioral, Educational, Economic, Business and Industrial Engineering.  ISSN 2010-376X.  68, s 1956- 1961
• Azadmehr, Mehdi & Berg, Yngvar (2011). A band pass Auto-Zeroing Floating-Gate Amplifier, In Thomas Ea (ed.),  2011 Faible Tension Faible Consommation (FTFC).  IEEE conference proceedings.  ISBN 978-1-61284-646-0.  Paper.  s 83 - 86 Show summary

  In this paper we present a band pass Auto-Zeroing Floating-Gate Amplifier (AZFA). The amplifier is based on Pseudo Floating gate and in addition to gain, it offers frequency band adjustment. Both the low-frequency and high-frequency cutoffs are controlled electronically, thus the amplifier can be used in design of various time continues filters. The AZA enjoys low component spread and compactness, containing only small size transistors and capacitors.

• Azadmehr, Mehdi & Berg, Yngvar (2011). A bi-directional auto-zeroing floating-gate amplifier, In Valeri Mladenov & Olga Martin (ed.),  Recent researches in circuits, systems, mechanics and transportation systems : Proceedings of the 10th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing (CSECS '11) : Proceedings of the 7th WSEAS International Conference on Applied and Theoretical Mechanics (MECHANICS '11) : Proceedings ot the 2nd International Conference on Automotive and Transportation Systems (ICAT '11) : Montreux, Switzerland, December 29-31, 2011.  World Scientific and Engineering Academy and Society.  ISBN 978-1-61804-062-6.  paper.  s 70 - 75 Show summary

  In this paper we present a bi-directional Auto-Zeroing Floating-gate Amplifier(AZFA). Due to gain and possibility of frequency band adjustment in both directions, the circuit is suited for designing bi-directional analog filters and amplifiers. The amplifier has different properties in each direction regarding frequency band and gain. The operation direction is controlled by swapping the V DD and GND. The AZFA enjoys low component spread and compactness, containing only minimum size transistors and capacitors. These properties in addition to bi-directionality of the circuit can result in more compact systems.

• Azadmehr, Mehdi & Berg, Yngvar (2011). Current-starved pseudo floating-gate filters, In Olfa Kanoun (ed.),  Transactions on systems, signals and devices : issues on sensors, circuits & instrumentation.  Shaker Verlag.  ISBN 978-3-8440-0678-0.  Paper.  s 381 - 399 Show summary

  In this paper we present different types of active filters designed using analog Current-Starved Pseudo Floating-Gate (CSPFG) inverters. We show how all types of filters (low pass, high pass, band pass and band reject) can be designed using only a combination of capacitors and CSPFG inverters, resulting in areasaving circuits suited for VLSI and ULSI circuit design. All the filters presented are tunable, allowing band adjustment using a bias voltage. Typical applications are detection of high frequency components in sensory signals and in radio frequency signal processing. AC simulations of the circuits are presented to show that these circuits are suited for high performance filter design. In addition, the open-loop gain of the CSPFG inverter is examined.

• Berg, Yngvar (2011). Differential static ultra low-voltage CMOS flip-flop for high speed applications, In Valeri Mladenov & Olga Martin (ed.),  Recent researches in circuits, systems, mechanics and transportation systems : Proceedings of the 10th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing (CSECS '11) : Proceedings of the 7th WSEAS International Conference on Applied and Theoretical Mechanics (MECHANICS '11) : Proceedings ot the 2nd International Conference on Automotive and Transportation Systems (ICAT '11) : Montreux, Switzerland, December 29-31, 2011.  World Scientific and Engineering Academy and Society.  ISBN 978-1-61804-062-6.  paper.  s 134 - 137 Show summary

  In this paper we present a simple ultra low-voltage and high speed D flip-flop. The delay of the static differential flip-flop presented is less than 12% compared to conventional differential CMOS flip-flops. The presented circuits have been simulated using Hspice and are valid for 90nm TSMC CMOS process. The proposed high-speed and ultra low-voltage flip-flop can be used for any digital low-voltage CMOS application.

• Berg, Yngvar (2011). NOVEL CLOCKED SEMI-FLOATING-GATE DIFFERENTIAL TRANSCONDUCTANCE AMPLIFER FOR ULTRA-LOW VOLTAGE ANALOG DESIGN, In Oliver Mazouffe (ed.),  Proceedings of the IEEE NEWCAS Conference.  IEEE conference proceedings.  ISBN 978-1-61284-136-6.  Kapittel.  s 285 - 288
• Berg, Yngvar (2011). NOVEL HIGH SPEED DIFFERENTIAL CMOS FLIP-FLOP FOR ULTRA LOW-VOLTAGE APPICATIONS, In Oliver Mazouffe (ed.),  Proceedings of the IEEE NEWCAS Conference.  IEEE conference proceedings.  ISBN 978-1-61284-136-6.  Kapittel.  s 241 - 244
• Berg, Yngvar (2011). ULTRA LOW-VOLTAGE AND HIGH-SPEED CMOS FULL ADDER USING FLOATING-GATES AND MULTIPLE-VALUED LOGIC. Proceedings - International Symposium on Multiple-Value Logic (ISMLV).  ISSN 0195-623X.  s 259- 262 . doi: 10.1109/ISMVL.2011.11
• Berg, Yngvar (2011). Ultra-Low-Voltage and High-Speed CMOS Full Adder Using the Floating Gates and Multiple-Valued Logic, In  Proceedings of the IEEE Symposium on Multiple-Valued Logic (ISMVL 2011).  IEEE conference proceedings.  ISBN 978-0-7695-4405-2.  Kapittel.  s 259 - 262
• Berg, Yngvar & Azadmehr, Mehdi (2011). Symmetric autozeroing floating-gate transconductance amplifier for ultra low-voltage applications, In Valeri Mladenov & Olga Martin (ed.),  Recent researches in circuits, systems, mechanics and transportation systems : Proceedings of the 10th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing (CSECS '11) : Proceedings of the 7th WSEAS International Conference on Applied and Theoretical Mechanics (MECHANICS '11) : Proceedings ot the 2nd International Conference on Automotive and Transportation Systems (ICAT '11) : Montreux, Switzerland, December 29-31, 2011.  World Scientific and Engineering Academy and Society.  ISBN 978-1-61804-062-6.  paper.  s 129 - 133 Show summary

  In this paper we discuss the symmetric autozeroing ultra low-voltage transconductance amplifier and present some applications. The autozeroing performed by all ULV circuits is important to reduce the impact of noise and especially avoid power supply noise in mixed signal low-voltage CMOS circuits. The simulated data presented is relevant for a 90nm TSMC CMOS process

• Berg, Yngvar & Mirmotahari, Omid (2011). Novel static differential ultra low-voltage and high speed domino CMOS logic, In Valeri Mladenov & Olga Martin (ed.),  Recent researches in circuits, systems, mechanics and transportation systems : Proceedings of the 10th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing (CSECS '11) : Proceedings of the 7th WSEAS International Conference on Applied and Theoretical Mechanics (MECHANICS '11) : Proceedings ot the 2nd International Conference on Automotive and Transportation Systems (ICAT '11) : Montreux, Switzerland, December 29-31, 2011.  World Scientific and Engineering Academy and Society.  ISBN 978-1-61804-062-6.  paper.  s 138 - 142 Show summary

  In this paper we present a novel static differential ultra low-voltage (ULV) CMOS logic style. Simulated data for the logic style is presented and compared to related ULV logic styles and complementary CMOS gates. The proposed logic style is aimed for high speed serial adders in ultra low-voltage applications. In terms of energy delay product (EDP) the logic style offers a significant improvement compared to complementary CMOS. The proposed differential ULV logic style offers improved noise margin compared to simpler ULV logic styles. The simulated data presented is obtained using Hspice simulator and applying a 90nm TSMC CMOS process.

• Berg, Yngvar & Mirmotahari, Omid (2011). Static ultra low-voltage and high performance CMOS NAND and NOR gates, In Valeri Mladenov & Olga Martin (ed.),  Recent researches in circuits, systems, mechanics and transportation systems : Proceedings of the 10th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing (CSECS '11) : Proceedings of the 7th WSEAS International Conference on Applied and Theoretical Mechanics (MECHANICS '11) : Proceedings ot the 2nd International Conference on Automotive and Transportation Systems (ICAT '11) : Montreux, Switzerland, December 29-31, 2011.  World Scientific and Engineering Academy and Society.  ISBN 978-1-61804-062-6.  paper.  s 143 - 146 Show summary

  In this paper we examine the robustness and performance of static ultra low-voltage CMOS binary logic. The logic gates presented are designed using semi floating-gate transistors and resembles domino CMOS. The performance and robustness of different logic gates are examined and compared to complementary and domino CMOS logic.

• Berg, Yngvar & Mirmotahari, Omid (2011). Ultra low-voltage CMOS current mirrors. Analog Integrated Circuits and Signal Processing.  ISSN 0925-1030.  68(2), s 219- 232 . doi: 10.1007/s10470-011-9607-8
• Azadmehr, Mehdi & Berg, Yngvar (2010). An auto-zeroing current-starved floating-gate band pass filter, In Anthony Constantinides & Sanjit K. Mitra (ed.),  Proceedings of the 4th INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS, CONTROL AND SIGNAL PROCESSING.  IEEE Signal Processing Society.  ISBN 978-1-4244-6286-5.  Paper. Show summary

  In this paper we present Auto-Zeroing Current-Starved Floating-Gate Amplifier(AZCSA). In addition to gain, the amplifier allows frequency band adjustment, suited for designing time-continuous analog filters. The Auto-Zeroing Current-Starved Floating-Gate Amplifier(AZCSA) is based on two previously presented floating-gate amplifiers. The AZCSA uses the advantages of these two amplifiers regarding the frequency band adjustment to improve the possibility of adjusting the lowest and highest cut-off frequencies. The AZCSA enjoys low component spread and compactness, containing only minimum size transistors and capacitors. The simulations presented in this paper are valid for the 90 nm CMOS transistor models from STM having a VDD equal to 1.2 V and threshold voltage of 0.25 V.

• Berg, Yngvar (2010). LOW VOLTAGE SEMI FLOATING-GATE BINARY TO MULTIPLE-VALUE AND MULTIPLE-VALUE TO BINARY CONVERTERS, In Roy Sterritt (ed.),  The 40th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2010).  IEEE Press.  ISBN 978-0-7695-4024-5.  Kapittel.  s 79 - 82
• Berg, Yngvar (2010). Low Voltage Semi Floating-Gate Binary to Multiple-Value and Multiple-Value to Binary Converters. Proceedings - International Symposium on Multiple-Value Logic (ISMLV).  ISSN 0195-623X.  s 79- 82 . doi: 10.1109/ISMVL.2010.22
• Berg, Yngvar (2010). NOVEL HIGH SPEED AND ULTRA LOW VOLTAGE CMOS FLIP-FLOPS, In Enrico Macii (ed.),  Proceedings of IEEE International Conference on Electronics, Circuits and Systems.  IEEE conference proceedings.  ISBN 978-1-4244-8156-9.  Kapittel.  s 298 - 301
• Berg, Yngvar (2010). NOVEL ULTRA LOW VOLTAGE SEMI FLOATING-GATE PASSBAND TRANSCONDUCTANCE AMPLIFIER, In Edward Gatt (ed.),  15th IEEE Mediterranian Electromechanical Conference (MELECON 2010).  IEEE Press.  ISBN 9781424457946.  Kapittel.  s 286 - 289
• Berg, Yngvar (2010). NOVEL ULTRA LOW VOLTAGE TRANSCONDUCTANCE AMPLIFIER, In Amara Amara (ed.),  Proceedings of the IEEE international symposium on circuits and systems 2010.  IEEE conference proceedings.  ISBN 978-1-4244-5309-2.  Kapittel.  s 1244 - 1247
• Berg, Yngvar (2010). NOVEL ULTRA LOW-VOLTAGE AND HIGH SPEED DOMINO CMOS LOGIC, In José I. Hidalgo (ed.),  2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SOC 2010).  IEEE conference proceedings.  ISBN 978-1-4244-6470-8.  Kapittel.  s 225 - 228
• Berg, Yngvar (2010). Novel ultra low voltage semi floating-gate passband transconductance amplifier. IEEE Mediterranean Electrotechnical Conference.  ISSN 2158-8473.  s 286- 289
• Berg, Yngvar (2010). Novel ultra low voltage transconductance amplifier. IEEE International Symposium on Circuits and Systems proceedings.  ISSN 0271-4302.  s 1244- 1247
• Berg, Yngvar (2010). STATIC ULTRA-LOW-VOLTAGE HIGH-SPEED CMOS LOGIC AND LATCHES, In José I. Hidalgo (ed.),  2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SOC 2010).  IEEE conference proceedings.  ISBN 978-1-4244-6470-8.  Kapittel.  s 115 - 118
• Berg, Yngvar (2010). ULTRA LOW VOLTAGE AND HIGH SPEED CMOS FLIP-FLOP USING FLOATING-GATES, In José I. Hidalgo (ed.),  2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SOC 2010).  IEEE conference proceedings.  ISBN 978-1-4244-6470-8.  Kapittel.  s 111 - 114

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• Dadashi, Ali; Berg, Yngvar & Mirmotahari, Omid (2017). Fast-settling, energy-efficient, amplifier for high-resolution LCD displays.
• Dadashi, Ali; Berg, Yngvar & Mirmotahari, Omid (2016). A High-Performance CMOS Modified Amplifier.
• Dadashi, Ali; Mirmotahari, Omid & Berg, Yngvar (2016). Domino Dual­Rail, High­Speed, NOR Logic, with 300mV supply in 90 nm CMOS Technology.
• Marchetti, Luca; Mirmotahari, Omid; Berg, Yngvar & Azadmehr, Mehdi (2016). A discrete implementation of a bidirectional circuit for actuation and read-out of resonating sensors.
• Marchetti, Luca; Mirmotahari, Omid; Berg, Yngvar & Azadmehr, Mehdi (2016). Bidirectional front-end for piezoelectric resonator.
• Mirmotahari, Omid; Dadashi, Ali & Berg, Yngvar (2016). High-speed dynamic dual-rail ultra low voltage static CMOS logic operating at 300 mV.
• Dadashi, Ali; Mirmotahari, Omid & Berg, Yngvar (2015). Ultra-Low-Voltage, Semi-Floating-Gate, Domino, Dual-Rail, Nor Gate.
• Azadmehr, Mehdi & Berg, Yngvar (2011). A band pass Auto-Zeroing Floating-Gate Amplifier.
• Moradi, Farshad; Wisland, Dag T; Aunet, Snorre & Berg, Yngvar (2011). Ultra Low Power Digital Circuit Design for Wireless Sensor Network Applications. Series of dissertations submitted to the Faculty of Mathematics and Natural Sciences, University of Oslo.. 1121.

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