System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
LMC_HOME C:\EDA\Xilinx_ISE10.1\ISE\smartmodel\nt\installed_nt < data not available > < data not available > C:\EDA\Xilinx_ISE10.1\ISE\smartmodel\nt\installed_nt
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
< data not available > < data not available > .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
Path C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;
C:\EDA\CygwinPortable\App\Cygwin\bin;
C:\Program Files\PC Connectivity Solution\;
C:\MyPrograms\;
C:\EDA\Xilinx_ISE11.1\ChipScope\bin\nt;
C:\EDA\Xilinx_ISE11.1\common\bin\nt;
C:\EDA\Xilinx_ISE11.1\common\lib\nt;
C:\EDA\Xilinx_ISE11.1\EDK\bin\nt;
C:\EDA\Xilinx_ISE11.1\EDK\lib\nt;
C:\EDA\Xilinx_ISE11.1\PlanAhead\bin;
C:\EDA\Xilinx_ISE11.1\ISE\bin\nt;
C:\EDA\Xilinx_ISE11.1\ISE\lib\nt;
C:\EDA\Xilinx_ISE10.1\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;
C:\Program Files\MiKTeX 2.8\miktex\bin;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\MATLAB\R2008b\bin;
C:\Program Files\MATLAB\R2008b\bin\win32;
C:\Program Files\TortoiseSVN\bin;
c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
C:\EDA\ModelSimXEIII6.4b_starter\win32xoem;
C:\Program Files\CVSNT\
< data not available > < data not available > C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;
C:\EDA\CygwinPortable\App\Cygwin\bin;
C:\Program Files\PC Connectivity Solution\;
C:\MyPrograms\;
C:\EDA\Xilinx_ISE11.1\ChipScope\bin\nt;
C:\EDA\Xilinx_ISE11.1\common\bin\nt;
C:\EDA\Xilinx_ISE11.1\common\lib\nt;
C:\EDA\Xilinx_ISE11.1\EDK\bin\nt;
C:\EDA\Xilinx_ISE11.1\EDK\lib\nt;
C:\EDA\Xilinx_ISE11.1\PlanAhead\bin;
C:\EDA\Xilinx_ISE11.1\ISE\bin\nt;
C:\EDA\Xilinx_ISE11.1\ISE\lib\nt;
C:\EDA\Xilinx_ISE10.1\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;
C:\Program Files\MiKTeX 2.8\miktex\bin;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\MATLAB\R2008b\bin;
C:\Program Files\MATLAB\R2008b\bin\win32;
C:\Program Files\TortoiseSVN\bin;
c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
C:\EDA\ModelSimXEIII6.4b_starter\win32xoem;
C:\Program Files\CVSNT\
XILINX C:\Xilinx\13.1\ISE_DS\ISE\ < data not available > < data not available > C:\Xilinx\13.1\ISE_DS\ISE\
XILINX_DSP C:\EDA\Xilinx_ISE11.1\DSP_Tools\nt < data not available > < data not available > C:\EDA\Xilinx_ISE11.1\DSP_Tools\nt
XILINX_EDK C:\EDA\Xilinx_ISE11.1\EDK < data not available > < data not available > C:\EDA\Xilinx_ISE11.1\EDK
XILINX_PLANAHEAD C:\EDA\Xilinx_ISE11.1\PlanAhead < data not available > < data not available > C:\EDA\Xilinx_ISE11.1\PlanAhead
XIL_MAP_LOCWARN 1 < data not available > < data not available > 1
XIL_PROJNAV_OUTPUT_LOG C:/WORK/GoAhead_Tutorials/HelloWorld/static/projnav.log < data not available > < data not available > C:/WORK/GoAhead_Tutorials/HelloWorld/static/projnav.log
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   PAR_stress.prj  
-ifmt   mixed Mixed
-ofn   PAR_stress  
-ofmt   NGC NGC
-p   xc6slx16-3-csg324  
-top   PAR_stress  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-keep_hierarchy Keep Hierarchy Yes No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis NO No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets   Auto Auto
-fsm_extract   YES Yes
-fsm_encoding   Auto Auto
-safe_implementation   No No
-fsm_style   LUT LUT
-ram_extract   Yes Yes
-ram_style   Auto Auto
-rom_extract   Yes Yes
-shreg_extract   YES Yes
-rom_style   Auto Auto
-auto_bram_packing   NO No
-resource_sharing   YES Yes
-async_to_sync   NO No
-use_dsp48   Auto Auto
-iobuf   YES Yes
-max_fanout   100000 100000
-bufg   16 16
-register_duplication   YES Yes
-register_balancing   No No
-optimize_primitives   NO No
-use_clock_enable   Auto Auto
-use_sync_set   Auto Auto
-use_sync_reset   Auto Auto
-iob   Auto Auto
-equivalent_register_removal   YES Yes
-slice_utilization_ratio_maxmargin   5 0
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise  
-mt Enable Multi-Threading off off
-ol Place & Route Effort Level (Overall) high std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Pentium(R) Dual-Core CPU T4200 @ 2.00GHz/2000 MHz <  data not available  > <  data not available  > Pentium(R) Dual-Core CPU T4200 @ 2.00GHz/2000 MHz
Host asus <  data not available  > <  data not available  > asus
OS Name Microsoft Windows XP Professional <  data not available  > <  data not available  > Microsoft Windows XP Professional
OS Release Service Pack 3 (build 2600) <  data not available  > <  data not available  > Service Pack 3 (build 2600)