top Project Status (10/02/2011 - 00:32:22)
Project File: static.xise Parser Errors: No Errors
Module Name: PAR_stress Implementation State: Mapped
Target Device: xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 13.1
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 4,999 18,224 27%  
    Number used as Flip Flops 4,999      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 4,999 9,112 54%  
    Number used as logic 4,999 9,112 54%  
        Number using O6 output only 4,999      
        Number using O5 output only 0      
        Number using O5 and O6 0      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
Number of occupied Slices 1,250 2,278 54%  
Number of LUT Flip Flop pairs used 4,999      
    Number with an unused Flip Flop 0 4,999 0%  
    Number with an unused LUT 0 4,999 0%  
    Number of fully used LUT-FF pairs 4,999 4,999 100%  
    Number of unique control sets 1      
    Number of slice register sites lost
        to control set restrictions
1 18,224 1%  
Number of bonded IOBs 2 232 1%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 0 248 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Sep 30 11:57:19 2011   
Translation ReportCurrentFri Sep 30 11:57:30 2011   
Map ReportCurrentFri Sep 30 11:58:39 2011   
Place and Route ReportCurrentFri Sep 30 11:59:12 2011004 Infos (4 new)
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentFri Sep 30 11:59:25 2011   
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentSun Oct 2 15:38:43 2011

Date Generated: 10/02/2011 - 16:41:22