| top Project Status (10/02/2011 - 00:32:22) | |||
| Project File: | static.xise | Parser Errors: | No Errors |
| Module Name: | top | Implementation State: | Translated |
| Target Device: | xc6slx16-3csg324 |
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| Product Version: | ISE 13.1 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slice Registers | 5250 | 18224 | 28% | |
| Number of Slice LUTs | 5362 | 9112 | 58% | |
| Number of fully used LUT-FF pairs | 5230 | 5382 | 97% | |
| Number of bonded IOBs | 14 | 232 | 6% | |
| Number of BUFG/BUFGCTRLs | 2 | 16 | 12% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Mon Oct 3 12:37:05 2011 | 0 | 36 Warnings (0 new) | 20 Infos (0 new) | |
| Translation Report | Current | Mon Oct 3 12:37:16 2011 | ||||
| Map Report | Out of Date | Sun Oct 2 15:37:11 2011 | 0 | 6 Warnings (0 new) | 9 Infos (0 new) | |
| Place and Route Report | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | Out of Date | Sun Oct 2 15:38:43 2011 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Log File | Out of Date | Sun Oct 2 15:38:43 2011 | |