FPGA Reconfiguration for Reducing Power Consumtion

For many digital systems, reducing the power consumption is the most important design objective. Optimizing the power consumption is a general issue and not only relevant for battery powered systems. For example, the cost of powering a server and the corresponding cooling can easily overtop its purchase price.

This master thesis is about using runtime reconfiguration on FPGAs (Field Programmable Gate Arrays) to reduce the power consumption of a network processing system running on an FPGA board.