Advances and Trends in Dynamic Partial Run-time Reconfiguration

Advances and Trends in Dynamic Partial Run-time Reconfiguration

Abstract

The progress in silicon industry has resulted in a tremendous increase in device capacity of FPGAs.
Now, the smallest devices of the upcoming Altera Stratix-5 FPGAs as well as the announced
Xilinx Virtex-7 FPGAs provide more than double the amount of logic and embedded memory
as the flagship devices of the one decade old Stratix or Virtex-II series FPGAs.
By passing the one million LUTs border, high density FPGAs are sufficient to
host 250 softcore CPUs plus the required peripherals.

Bibtex

@INPROCEEDINGS{dagstuhl10koch,
        AUTHOR             = {{Koch}, {Dirk} and {Torresen}, {Jim}},
        ADDRESS            = {Schloss Dagstuhl, Germany},
        BOOKTITLE          = {Dagstuhl-Seminar 10281: Dynamically Reconfigurable Architectures},
        MONTH              = jul,
        PAGES              = {6},
        PUBLISHER          = {Internationales Begegnungs- und Forschungszentrum f{\"u}r Informatik (IBFI), Schloss Dagstuhl, Germany},
        TITLE              = {{Advances and Trends in Dynamic Partial Run-time Reconfiguration}},
        YEAR               = {2010},
        DATE               = {Juli 11--16},
        ISSN_ISBN          = {1862-4405}
}