The speed of the memory system on a processor is vital for many types of workloads, such as deep-learning workflows and physics-based computer simulations. When several cores on a multicore CPU simultaneously use the memory system, competition between the cores for the available memory bandwidth is inevitable. In real-life situations, different cores have different memory traffic loads. This heterogeneity in traffic load, combined with the hardware heterogeneity in the memory system, creates a challenge to accurately predicting how much time each core needs to complete its memory traffic load. Without accurate predictions of the memory operations, it is then impossible to expect how much time a computational task needs.
This master aims to improve the "two-phase" model (published in 2025), which suits very well for the situation of having only one-level competition between the cores on a multiprocessor. There are however at least two levels of competition on a multiple processor from AMD, so the "two-phase, one-level" performance model will not work properly. For instance, the generation-5 Epyc processor organises 8 cores together as a core complex, and a processor is composed of multiple core complexes (see the figure above for an example). Additionally, the core complexes may be organized into several so-called NUMA domains.
The master student is expected to derive a new performance model specifically targeting AMD processors, such that given individual memory traffic amount per core as input, the new model is able to predict the time usage of each core, by considering the time-varying and heterogeneous competition both within the core complexes and between them.
The project will be carried out in the following steps:
- Familiarize with the existing "two-phase, one-level" performance model, as well as the other existing "staircase" performance model.
- Implement simple memory-bandwidth benchmarks (based on the STREAM benchmark), for the purpose of pinpointing the amount of memory bandwidth available to each core complex when the number of competing complexes changes. These benchmarks assume that the number of active cores per complex is identical.
- Modify the simple benchmarks from above by allowing different number of active cores per complex.
- Derive a multi-level, multi-phase performance model, based on the observations and measurements obtained from the newly developed benchmarks, while reusing relevant parts from the "two-phase" model and/or the "staircase" model.
- Validate the accuracy of the multi-level, multi-phase performance model by applying it to realistic computational examples (such as sparse matrix-vector multiplications with a very uneven work distribution among the CPU cores), by comparing the model predictions against the actual time measurements on several types of AMD multicore CPUs.
- Make informed decisions about (heterogeneous) work division and the ideal number of cores to be used (per core complex), with the goal of improving the overall memory system performance of AMD multicore CPUs.
Required background knowledge and skills:
- Basic knowledge in C programming
- Interest in learning level-low hardware details of multicore CPUs
- Interest in learning simple parallel programming (OpenMP programming)
- Interest in learning simple mathematical modeling (using very simple functions)
References:
- AMD White Paper: "5TH GEN AMD EPYC™ PROCESSOR ARCHITECTURE".
- Johannes Langguth, James David Trotter, & Xing Cai (2025). Modelling load imbalance in shared memory multicore systems. Proceedings of the SC '25 Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis (pp. 1433–1441).
- Andreas Thune, Sven- Arne Reinemo, Tor Skeie, & Xing Cai (2023). Detailed modeling of heterogeneous and contention-constrained point-to-point MPI communication. IEEE Transactions on Parallel and Distributed Systems, 34(5), 1580–1593.
- STREAM: Sustainable Memory Bandwidth in High Performance Computers.