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Software models of neural networks (NN) these days are used everywhere in artificial intelligence (AI) applications. As they are computationally rather resource and power demanding, hardware support for neural networks is in high demand. GPUs (i.e. graphic cards) for example, have an architecture that can be exploited for efficient neural network computations. THIS project however, wants to be look into hardware that is even more specifically dedicated to efficient neural network computations. Specifically we want to investigate FPGA implementations of asynchronous spiking neural networks.
Specific for SNN is that the timing of the individual nerve pulses between neurons carries the information, rather than for instance the level or value of a signal. One specific encoding scheme is the 'time to first spike' encoding proposed by Simon Thorpe, which this project will employ at least as a starting point to emulate a more traditional artificial neural network (ANN) with a SNN. Here the delay of a pulse/spike after a reset of the spike emitting neuron indicates an analog value. A receiving neuron has to measure that delay to decode the value sent by the emitting neuron(s). In turn, the receiving neuron can do some computation with all these inputs, typically in an ANN a summation of all inputs and then a 'sigmoid' activation function on that sum to determine it's own next output, i.e. the delay for its own next spike.
The network of interconnections bewteen neurons can be implemented using the so called address event representation (AER), i.e. an asynchronous communication protocol capable of sending events (i.e. the spikes) in real time in a network betweeen many emitters and receivers.
Using the above idea as a starting point the project will also investigate the most recent developments in SNNs and evaluate other approaches to implementing a classical ANN as an SNN.
Experience with VHDL/Verilog programming and/or ANNs (Error back propagation and multi layer perceptrons) will be advantageous.