RISC-V is an open instruction set architecture without a bound hardware microarchitecture. Processors made using different degrees of serialization can still use the same machine code. The openness and availability of compilers makes the use of RISC-V compelling for testing. RISC-V also has multiple optional instruction extensions that can be used for different purposes.
In this thesis you will explore and categorize various degrees of serialization of RISC-V processors using FPGAs. Serialization can vary from methods such as processing a single bit at a time, in an ALU or for example four by four rather than one to leverage typical FPGA features such as lookuptables, decicated carry logic and multipliers. Serialization can be a bottleneck, but it can also be used to achieve high degree of parallelism, which may in turn be used to create great throughput with large data. Serialized arithmetic algorithms can also be used to save power when only sparse computation is required.
Exploring what it takes to achieve such benefits and map both theoretical and practical limitations can be a part of this thesis. A starting point will be to read about serial processor architectures that has been made, such as the aforementioned ZPU and serv processors, and then create and test your own processor(s) to compare and map how different properties become relevant for different settings.