Nettsider med emneord «Simulating Runtime Reconfigurable Systems»

Sorting is an often used and computing intensive kernel in database systems. The amount and the size of keys to be sorted can easily result in datasets of several gigabytes. The keys may represent simple numbers or even data structures with different kind of types.

Sorting is an ideal application to be accelerated by FPGAs (Field Programmable Gate Arrays) that can be adapted to different sorting tasks at runtime. Furthermore, runtime reconfiguration is useful to speed-up different phases during the sorting.

FPGAs (Field Programmable Gate Arrays) are devices that can be customized with various circuits after manufacturing the chip. Some FPGAs allow for changing fractions of the circuitry loaded to the device while keeping the rest of the system running. This process is called partial runtime reconfiguration. Among manifold further advantages, this technique allows to implement systems on smaller - and therefore cheaper and less power hungry - chips. However, designing runtime reconfigurable systems is difficult, becau-se of a lack in adequate verification techniques.

Throughout this thesis, a simulation framework has to be designed that is in particular capable of simulating effects originating from partially reconfiguring a system on an FPGA. The simulation will be verified with original test data from an FPGA.