Faglige interesser
A highly motivated Electronics engineer with a PhD in Electronics and MSci in Nano-electronics. In-depth understanding of CMOS digital/analogue circuit design, hardware testing and instrumentation, embedded firmware development, PCB design, and radiation effects in electronics. Excellent FPGA and Microcontroller programming skills.
Background
WORK EXPERIENCE
Company: Axicon
Position: Hardware System Engineer Sep 2023–Aug 2024
I continued my career journey to develop smart electronics which will help Norwegian Public Road Administration to achieve their Vision Zero ambition. The tasks were related to the development of electronics which will eliminate road fatalities caused by excessive vehicle speed. Some key responsibilities were:
• Hardware System development.
• In-house production and service from idea to final product.
• R&D solutions for Automatic Traffic control.
• Contribute to create and maintain good and up-to-date documentation.
• Modernize co-existing solutions.
• Investigate replacements for "end-of-life" components and ensure that the quality of new components meets our requirements both in lab and out in the field.
• Transform customer requirements into final products with the latest technology solutions.
Company: Roadguard
Position: Senior Electronics Engineer Nov 2022 – Aug 2023
I worked as a Senior Electronics Engineer in a start-up called Roadguard. I was responsible for the research and development of electronic systems that will be used in the Roadguard’s optical tire scanners. These scanners will be used to prevent traffic accidents on the Norwegian roads caused by worn tires. During my short period at Roadguard, I developed three successful PCBs to facilitate triggering for various external components in the sensor unit and polished my embedded programming skills using stm32 microcontroller which interfaced with Acconeer’s object detection radar chip. Several on-field tests were performed to evaluate the performance of system and radar chip with respect to various vehicle speeds.
Company: Numascale
Position: Hardware Engineer Jan 2019 – Nov 2022
I worked as Hardware Engineer at NumaScale AS, located in Oslo. The tasks were related to the development of next-generation Node Controllers ASICs, which are used in cache-coherent shared memory computers. The Numascale node controller roadmap is in cadence with Intel’s generations of server CPUs. Node Controller ASICs enables system vendors to build up to 32 sockets single node scale-up servers. Major applications are SAP HANA, Big Data Analytics, Graph Processing, Deep Learning, and general purpose HPC applications. Main responsibilities are:
• RTL design and sanity testbench with System Verilog.
• Top level tests using UVM framework.
• Failure-In-Time (FIT) estimations for radiation induced soft errors, mainly due to alpha particles and cosmic rays.
• TCL scripting for synopsis tool to automatically determine number of soft error protected flops in the design.
• Provide and implement soft error mitigation techniques to meet FIT target and document FIT calculations methodology for future projects.
• Discuss and implement worst case test scenarios together with the architects in to obtain maximum toggling activities for power consumption estimation of the DUT, dump toggling activities in FSDB format using VCS Synopsis tool which is further used by the back-end team to calculate power consumption.
• Assist verification team in both functional and code coverage closure.
• Improve and write user documentation for Numascale IPs.
Lab Assistant
- Course responsible for FYS4260 - Microsystems and electronic packaging and interconnection technologies. (Spring 2014)
- Lab Assistant for INF5460 - Electrical noise – counter measures and calculation. (Autumn 2014)
- Lab Assistant for FYS1120 - Electromagnetism. (Autumn 2015, 2016).
- Lab Assistant for FYS2160 - Thermodynamics and statistical physics. (Autumn 2015, 2016)
EDUCATION
PhD: Electronics University of Oslo, Norway 2013- 2020
Thesis: “Exploring Single Event Effects in the ALICE (A Large Ion Collider Experiment) SAMPA chip”.
The thesis was carried out as part of the ALICE collaboration at CERN. The main project was to design a new front-end chip (SAMPA) to readout data from various detectors of the ALICE (A Large Ion Collider Experiment). ALICE is one of the main detector experiments at the LHC (Large Hadron Collider) at CERN.
The main objective of my thesis was to investigate the radiation tolerance and possible mitigation actions for the SAMPA chip. This involved an analysis of the chip design to identify critical parts and determine their sensitivity to radiation, an analysis of the radiation environment where SAMPA chip will be installed, implementation of possible mitigation actions, and irradiation campaigns to characterize radiation sensitivity of various prototypes of the SAMPA chip.
I was entirely responsible for tasks related to the radiation hardness assurance of the SAMPA prototypes. It mainly consisted of:
i. Planning various campaigns according to the projected submission deadlines of the prototypes.
ii. Ensuring proper preparation and execution of the campaigns.
iii. Analysis of acquired results from the campaigns.
I accomplished expertise to perform a successful irradiation campaign which involves several tasks, such as appropriate facility selection, equipment transport, physical setup preparation (reliable cables and connectors), test setup development, ensure continuous remote data acquisition for several hours of particle beam during the campaign, and the ability to execute critical actions under time-critical situations during the campaigns. The campaigns were performed at different beam facilities, and I adapted our irradiation test setup efficiently to communicate with the available interfaces at these facilities. The main concern of these campaigns was to qualify SAMPA chip against Single Event Effects (SEE). This was accomplished by developing two independent test setups to identify both soft and hard SEEs during the campaigns.
MSci: Nano-electronics University of Oslo, Norway 2008-2013
Thesis: “NP domino logic gates for Ultra Low Voltage and High-Speed Applications”. Implementing ultra-low voltage digital circuits. The challenge was to combat traditional trade-offs of CMOS transistors like speed and low power while keeping the robustness at an acceptable level. Working with the thesis polished my skills in transistor level IC design and developed a thorough understanding of the digital circuits and their functionality within VLSI circuits.
Samarbeid
CERN