Nettsider med emneord «Image Sensor»
This project wants to explore possibilities to read out pixel data of a CMOS image sensor (CIS) non-destructively (i.e. without emptying the pixel of its photo charge) while the exposure is still ongoing. This will allow adaptive exposure time (or the adjustment of other exposure parameters) 'on the fly' leading to better quality images, without having to retake the image multiple times and thus wasting precious time in high speed applications.
CMOS image sensors (CIS) are widely adopted in many application fields, such as industry control system, automotive, consumer electronics, surveillance system, and so on. Inside of a CIS, a column-ADC based readout architecture is commonly employed because of its high-speed and low-noise readout capability. To improve readout speed and noise performance of column-parallel readout architecture, a compact and efficient column ADC structure is desired. A VCO-based voltage-to-frequency or voltage-to-digital converter is a promising candidate for real column level ADC that could be contained completely inside of column array.
Having an accurate and reliable model for electron generators is important when it comes to design of blocks dealing with elements such as photodiodes (PD) or ISFETs. Common way to simulate/analyse this type of blocks is to replace the photo diode with a current source. This may result in some unrealistic voltage developments on sensitive nodes or leakages not expected. Recent advances in photo-sensors field brings the need for an appropriate PD model under the spotlight.
CMOS image sensors (CIS) are widely adopted in various applications for example mobile and automotive cameras. As the application expanding their functionality to motion sensing and autonomous driving, the applications keep demanding for higher resolution and faster operating CIS while maintaining the power budget. Therefore, implementing CIS with low-noise and low-power analogue front end (AFE) is essential. Moreover, in an advanced process, conventional analogue design approaches have many challenges such as lower intrinsic gain of devices, and smaller headroom for operation. Therefore, a new structure is highly required to meet the requirements and to solve the challenges. A current-reusing architecture, as the name self-explained, utilizes the supply current to generate transconductance of both PMOS and NMOS. Therefore, the structure could improve gain, bandwidth, and noise characteristics comparing to the conventional analogue stages. For this reason, architecture is a suitable candidate for the solution.
Modern CMOS image sensor (CIS) are realized in highly specialized semiconductor production processes that provide microscopic photo pixels allowing extremly high quality photo-sensing: the noise level is actually measured in just a few quanta of electron charges. However, these production processes are generally a well guarded secret, costly, and not easily available for academic research groups. Thus, we have for some time used general purpose CMOS processes instead to make experimental image sensors. That is possible becasue basically any PN-diode on a CMOS chip is sensitive to light and can be repurposed as a light sensor.