Currently the main options are related to verification components (VVC) for the open-source Universal VHDL Verification Methodology (UVVM framework).
The first option is developing and testing VVC components for advanced and safety critical purposes, such as space, automotive or defense applications.
Developing VVC for advanced, safety critical systems (Norwegian)
The second option is to explore how co-simulation can and should be used together with VVC components made in VHDL.
Software-guided verification using co-simulation with UVVM (Norwegian)
Central to both tasks is exploring and understanding how we can and should make verification components to facilitate ease of use, communication and efficiency during simulation.
Generally Inventas is open for suggestions that may align with their goals, which means other options may become available and each task can be tailored in several directions. Earlier I:RIS students has worked together with Inventas with topics such as ball bearing fault detection using neural networks on FPGA and compressed sensing for edge devices.