Nettsider med emneord «Hardware Linking for FPGAs»

Present design flows for digital hardware systems require many costly iterations for simulation, synthesis and the physical implementation on the chip. The productivity in designing such systems increases much slower than the progress in silicon industry, which is called the design productivity gap. Hence, the engineering cost of a product may overtake the production cost in the future. This holds especially for FPGAs (Field Programmable Gate Arrays), which are commonly used in lower volume products.

The aim of this master thesis is to develop and implement a component-based design methodology and a corresponding tool where systems are built with the help of predesigned components.  

The novel ReCoBus communication architecture allows to place reconfigurable modules in a relatively fine two-dimensional grid on FPGAs (Field Programmable Gate Arrays). This provides a significant utilization improvement for the undelaying host FPGA as compared to previous approaches. However, this implies that the corresponding modules are efficiently packed on the device.

The goal of this master thesis is to develop a module placer that automatically packs a set of given modules (specified by their geometry) on a definable grid. The placer should be able to deal with real world FPGA devices.