Snorre Aunet

• Yassin, Yahya Hussain; Jahre, Magnus; Kjeldsberg, Per Gunnar; Aunet, Snorre & Catthoor, Francky (2021). Fast and accurate edge computing energy modeling and DVFS implementation in GEM5 using system call emulation mode. Journal of Signal Processing Systems.  ISSN 1939-8018.  93(1), s 33- 48 Show summary

  Stringent power budgets in battery powered platforms have led to the development of energy saving techniques such as Dynamic Voltage and Frequency scaling (DVFS). For embedded system designers to be able to ripe the benefits of these techniques, support for efficient design space exploration must be available in system level simulators. The advent of the edge computing paradigm, with power constraints in the mW domain, has rendered this even more essential. Without a fast and accurate methodology for architecture simulation and energy estimation, the benefit of new ideas and solutions cannot be evaluated. In this paper, we propose a non-intrusive application controlled DVFS management implementation in the GEM5 simulator, used with GEM5’s system call emulation mode. We also propose a novel architecture independent energy model based on categorization of different measurable workload classes. Our energy model is parametrized and calibrated with power measurements on a SAM4L microcontroller board, containing an ARM Cortex M4 processor. Together with the GEM5 output statistics, the model accurately estimates the total energy consumption of our simulated system. The results from our modified GEM5 simulator are validated with representative signal processing applications. After correction of systematic offset errors, our results deviate with less than 4% compared to measurements from the SAM4L microcontroller. Our contributions in this paper can easily be tailored to other processor models in GEM5 and to future versions of GEM5. It will therefore enable system architects to explore new techniques and compare the improvements relative to existing architectures.

• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2020). An ultra low voltage subthreshold standard cell based memories for IoT applications, In Hadi Seyedarabi (ed.),  Proceedings, 28th Iranian Conference on Electrical Engineering.  IEEE conference proceedings.  ISBN 978-1-7281-7296-5.  vitenskapelig artikkel. Show summary

  In this paper, we have designed an ultra low voltage standard cell based memory (SCM) in the subthreshold domain. The SCM has been synthesized, placed and routed based on an ultra low voltage full custom standard cell library using 130 nm process technology, functional for subthreshold supply voltages as low as 140 mV, which is well below the supply voltages reported in the previous works of SCMs. This SCM has been designed based on the standard D-latch which holds data at a supply voltage as low as 170 mV. The designed SCM is functional for a temperature range of 27–50 °C applicable for implantable biomedical systems requiring small memory capacity. According to the simulations from the extracted netlist, the energy per bit access at Vdd=200 mV and 333 kHz frequency, suitable for many loT applications, is 1.54 fJ.

• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2020). Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology, In . IEEE (ed.),  2020 IEEE Nordic Circuits and Systems Conference (NorCAS).  IEEE.  ISBN 978-1-7281-9226-0.  kapittel. Show summary

  This study presents a comparative study of single, regular and flip well subthreshold SRAMs in 22 nm FDSOI technology. A 7T loadless SRAM cell with a decoupled read and write port has been used as a case study. Simulation results, based on the extracted netlist from layout, show that the speed of the flip well SRAM is significantly better than that of the single and regular well SRAMs. In terms of leakage current, single well is the best option. The regular well type has lower static noise margin (SNM) variability. Among all devices used (HVT, RVT, LVT and, SLVT) available in a commercially available 22 nm FDSOI technology, the best combination for minimizing energy per access is HVT devices as driver transistors and RVT for the rest of the transistors. This study may help designers to select an optimal architecture based on their application and performance requirements. The 22 nm FDSOI technology enables a wide range of back gate bias voltages to improve the read stability and write ability of the SRAMs and, hence, their minimum operating voltage and power consumption.

• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2020). Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders, In . IEEE (ed.),  2020 IEEE Nordic Circuits and Systems Conference (NorCAS).  IEEE.  ISBN 978-1-7281-9226-0.  kapittel. Show summary

  This paper designs and reports energy efficient subthreshold adders using 22 nm FDSOI technology. The dynamic body biasing technique and multi-threshold voltage devices have been used to match Pull up/Pull down networks (PUN/PDN). The post-layout simulation results show that the logic gates and full adder circuit based on dynamic body biasing are more robust than those with conventional body bias against process, voltage, and temperature (PVT) variations at ultra low supply voltages. The adder based on the conventional and dynamic body biasing techniques have achieved energy per addition of 0.23 fJ at Vdd =300 mV and 0.56 fJ at Vdd =140 mV, respectively. Compared to the other published subthreshold adders in [1] and [2], the energy per addition for our designed adders improved by 2.82X, 28.1X, respectively. The minimum operating supply voltage for dynamic and conventional body bias adders based on Monte Carlo simulations taking into account both mismatch and process variations are 140 and 200 mV, respectively. The area for conventional body biased adder has been reduced by 43.9 and 38.8 percent compared to those of the adders in [1] and [3], respectively.

• Låte, Even; Ytterdal, Trond & Aunet, Snorre (2020). An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V. IEEE Transactions on Circuits and Systems - II - Express Briefs.  ISSN 1549-7747. . doi: 10.1109/TCSII.2020.2966654 Show summary

  We propose architectural advances in low voltage, energy efficient, level shifters. A write assist circuit is introduced,to support up-conversion of deep subthreshold inputs. We also present an approach to reduce the leakage current in split signal output stages. A prototype was created in a 130 nm bulk CMOS process, and some samples were successfully tested for input voltages as low as 5 mV. For 10 measured samples, the mean functional, minimum, input voltage was 31.1 mV. By applying body bias to selected NMOS transistors to compensate for process and mismatch variation, the measured mean minimum input voltage was lowered to 14.3 mV. The leakage reduction in the split control output driver reduces the driver leakage by a factor of 8. The designed level shifter was found to be energy efficient compared to published structures, it consumed an average of 25.9 fJ per conversion in post-layout simulations and the delay was measured to 21.08 ns at 300 mV input signals.

• Låte, Even; Ytterdal, Trond & Aunet, Snorre (2020). Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping. IEEE Transactions on Very Large Scale Integration (vlsi) Systems.  ISSN 1063-8210.  28(10), s 2223- 2227 . doi: 10.1109/TVLSI.2020.3013139 Show summary

  This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally flipped during write operations to reach the more beneficial state for storage. A 1-kb SRAM block of low-voltage memory cells was implemented and manufactured in a 130-nm CMOS. The memory cells were made writable and read-stable at low supply voltages with a single-ended write and single-ended read structure using six multithreshold transistors that give rise to an asymmetric retention power. At a supply voltage of 350 mV, the content-dependent leakage power in the asymmetric memory cell is 23 times smaller when storing logic “1”s compared with logic “0”s. A derived statistical model suggests that the mean, wordwise, static power savings of the word-flipping scheme become 15.70% for 8-bit words of uniform bit probability. For the implemented SRAM macro, the mean improvement for the retention power is, including flip logic and decoder and driver overheads, found to be 14.69%. In boundary tests, by writing all words full of undesired values, the power saving becomes 80.37%, while writing all words full of desired values causes a power penalty of 6.14%. Measurement results confirm the improvement in retention power with a ten-chip mean improvement of 11.93% for the same data set.

• Christensen, Steinar Thune; Aunet, Snorre & Qadir, Omer (2019). A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural Networks, In Jari Nurmi; Peeter Ellervee; Kari Halonen & Juha Røning (ed.),  2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).  IEEE.  ISBN 9781728127699.  vitenskapelig artikkel. Show summary

  This paper presents a configurable, versatile and flexible architecture for hardware acceleration of convolutional neural networks (CNNs) that is based on storing and accumulating entire feature maps in local memory inside the accelerator. This has been done while aiming to be able to process any type of CNN while consuming as low power as possible and achieving the highest possible energy efficiency. Energy efficiency refers to the number of operations per unit energy (measured in Multiply-Accumulate operations per unit energy, MACs/s/W or MACs/J). Mainly, two different versions of the architecture have been synthesized and tested using different configurations of hardware parameters. It performs well when compared to the state-of-the-art, achieving an improved energy efficiency of over a factor 5 for select CNN layers. The most energy efficient configuration achieves 175 GMACs/s/W, while consuming 2.3 mW of power and occupying 585 KGEs (Kilo Gate Equivalents) of area at 1V supply voltage and a clock frequency of 100MHz.

• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2019). Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology, In Jari Nurmi; Peeter Ellervee; Kari Halonen & Juha Røning (ed.),  2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).  IEEE.  ISBN 9781728127699.  vitenskapelig artikkel. Show summary

  Abstract—This study presents a strategy to determine optimal body bias voltages for ultra low voltage digital circuits in the 22 nm Fully Depleted Silicon On Insulator Technology (FDSOI). The efficiency of body biasing for achieving high functional yield has been investigated by using reveres back bias voltages for HVT devices. The strategy has been evaluated through the design of an ultra low voltage Xor based adder at supply voltages varying from 140-160 mV and temperature range 27-50 °C at 1 kHz frequency. The adder under optimal body bias consumes 4.67 percent less energy than zero body bias at Vdd=150 mV and frequency of 1 kHz. The adder is fully functional functional for 1 k Monte Carlo simulations at optimal back bias voltage. The yield has improved by 0.4 percent in optimal back bias voltage compared to zero body bias. The results show the lowest Energy per cycle, variability and high functional yield for the obtained optimal body bias voltage. Also, additional analysis confirm the dependency of optimal body bias voltage on the switching activity and operating conditions for a given technology. We also show that the relative energy variability is larger than the delay variability over the back bias voltage range. Index Terms—optimal body bias, reverse back bias, HVT device, activity factor, variability, functional yield.

• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2019). Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder, In Jari Nurmi; Peeter Ellervee; Kari Halonen & Juha Røning (ed.),  2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).  IEEE.  ISBN 9781728127699.  vitenskapelig artikkel. Show summary

  Abstract—In this study, 8, 16 and 32 bits ultra low power, robust, Kogge Stone (KSA) and Ripple Carry (RCA) adders using available 130 nm CMOS bulk technology have been designed and analyzed at subthreshold supply voltages ranging from 140-160 mV and temperature range of 27-50 °C at 5 kHz frequency for implantable biomedical devices. Simulation results based on netlists extracted from layout confirm that with a marginal increase in the supply voltage of the RCA compared to that of the KSA adder at the same speed, the power consumption and energy per operation, as well as the area usage of the RCA is far less than KSA. For example, when increasing the supply voltage of the 8 bit RCA by 44 mV compared to that of the KSA adder, the energy per operation for the KSA is about 3.5 times higher than that of the RCA. We have investigated different RCA topologies and considered the minimum energy point varies with different topologies. In addition, in the case of low throughput applications, using the stacked inverters for the full adder will reduce the leakage current and the total energy per cycle of the circuit. For the Minority-3 based 32 bits RCA with stacked inverters, the energy per cycle improves 15 percent compared to that of Minority-3 based 32 bits RCA at Vdd = 150 mV. Index Terms—KSA, RCA, ultra low voltage, implantable biomedical devices, channel length upsizing, minimum energy point, stacked inverters.

• Seyedi, Azam; Aunet, Snorre & Kjeldsberg, Per Gunnar (2019). Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications, In Jari Nurmi; Peeter Ellervee; Kari Halonen & Juha Røning (ed.),  2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).  IEEE.  ISBN 9781728127699.  vitenskapelig artikkel. Full text in Research Archive.
• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2018). Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology, In Juri Mihhailov & Maksim Jenihhin (ed.),  Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).  IEEE.  ISBN 978-1-5386-7656-1.  paper. Full text in Research Archive.
• Låte, Even; Ytterdal, Trond & Aunet, Snorre (2018). A loadless 6T SRAM cell for sub- & near- threshold operation implementedin 28 nm FD-SOI CMOS technology. Integration.  ISSN 0167-9260.  63, s 56- 63 . doi: 10.1016/j.vlsi.2018.05.006 Full text in Research Archive. Show summary

  Most ultra low power SRAM cells operating in the sub and near threshold region deploy 8 or more transistors per storage cell to ensure stability. In this paper we propose and design a low voltage, differential write, single ended read memory cell that consists of a total of 6 transistors. The innovative idea is to bring the loadless 4-transistor latch into the realm of low voltage memory cells by exploiting features of the 28 nm FDSOI Process and by adding a 2-transistor readbuffer with a footer line. Stand-alone and on a system level, the cell is stable during read, write and hold operations and it has great write-ability due to its differential write and loadless nature. The single NWELL option in 28 nm FD-SOI allows the loadless core to have minimal device widths while greatly improving the time it takes to evaluate the read bit-line. The cell has, in this paper, been used in a 128 kb (2 17 ) SRAM in a 16 block configuration exploring 3 different types of logic libraries for the peripheral logic of the system. Depending on the application, the IO-peripheral logic may be implemented using either high threshold voltage transistors or low threshold voltage transistors in where the power consumption of the 128 kb system was found to range from 1.31 µW to 71.09 µW, the maximum operational frequency lies within 1.87 MHz and 14.97 MHz while the read energy varies from 13.08 to 75.21 fJ/operation/bit for a supply voltage of 350 mV. The minimum retention voltage of the loadless SRAM cell is found to be 230 mV covering 5σof variation with Monte Carlo simulations.

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2018). An Ultra-Low Voltage and Low-Energy Level Shifter in 28 nm UTBB-FDSOI. IEEE Transactions on Circuits and Systems - II - Express Briefs.  ISSN 1549-7747.  66(6), s 899- 903 . doi: 10.1109/TCSII.2018.2871637 Full text in Research Archive. Show summary

  Abstract—A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used along with poly and back-gate biasing techniques to achieve an adequate balance between the drive strength of the pull-up and the pull-down networks. Measurements showed that the lowest input voltage levels, which could be upconverted by the 10 chip samples, varied from 39 mV to 52 mV. Half of the samples could upconvert from 39 mV to 1 V. The simulated energy consumption of the level shifter was 5.2 fJ for an up-conversion from 0.2 V to 1 V and 1 MHz operating frequency.

• Låte, Even; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2017). Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI. Microprocessors and microsystems.  ISSN 0141-9331.  48, s 11- 20 . doi: 10.1016/j.micpro.2016.07.016 Show summary

  Nine D-type Flip-Flop (DFF) architectures were implemented in 28 nm FDSOI at a target, subthreshold, supply voltage of 200 mV. The goal was to identify promising DFFs for ultra low power applications. The single-transistor pass gate DFF, the PowerPC 603 DFF and the C2MOS DFF are considered to be the overall best candidates of the nine. The pass gate DFF had the lowest energy consumption per cycle for frequencies lower than 500 kHz and for supply voltages below 400 mV. It was implemented with the smallest physical footprint and it proved to be functional down to the lowest operating voltage of 65 mV in the typical process corner. During Monte Carlo (MC) process and mismatch simulations it was also found that the pass gate DFF is least prone to variations in both minimal setup- and minimal hold-time. Race conditions, during mismatch variations, occurred for the flip-flop that is constructed from NAND and inverter based multiplexers. The pass gate DFF is outperformed slightly when it comes to D-Q-based power-delay product and more significantly when it comes to the maximum clock frequency. The flip-flops having the shortest D-Q delays were the PowerPC 603 and the transmission gate D flip-flop, these also had the lowest D-Q-based power-delay of 26% and 30% respectively of that of the worst-case S2CFF power-delay product.

• Vatanjou, Ali Asghar; Låte, Even; Ytterdal, Trond & Aunet, Snorre (2017). Ultra-Low Voltage and Energy Efficient Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing. Microprocessors and microsystems.  ISSN 0141-9331.  56, s 92- 100 . doi: 10.1016/j.micpro.2017.11.002 Show summary

  Balancing the PMOS/NMOS strength ratio is a key issue to maximize the noise margin, and hence, the functional yield of CMOS logic gates and minimize the leakage energy per cycle in the subthreshold region. In this work, the PMOS/NMOS strength ratio was balanced using a poly-biasing technique in conjunction with back-gate biasing provided in a 28 nm fully depleted silicon on insulator (FDSOI) CMOS technology. A 32-bit adder based on minority-3 (min-3) gates and a 16-bit adder based on Boolean gates have been implemented. Chip measurement results of nine samples show highly energy efficient adders. The 32-bit and 16-bit adders achieved mean minimum energy points (MEP) of 20.8 fJ at 300 mV and 12.34 fJ at 250 mV, respectively. In comparison to adders reported in other works in the same technology, the energy per 1-bit addition of the 32-bit adder is improved by 37% . This improvement in energy consumption is 25% for the 16-bit adder. According to the measurement results of ten chips, the designed adders exhibited functionality down to supply voltages of 110 mV-125 mV, without body biasing. Additionally, the minimum Vdd of all the 32-bit adders based on minority-3 gates decreased to 80 mV by applying a reverse back bias voltage to the PMOS devices. One sample was functional at 79 mV with a 430 mV reverse back bias voltage applied to its PMOS devices.

• Hasanbegovic, Amir & Aunet, Snorre (2016). Heavy Ion Characterization of Temporal-, Dual- and Triple Redundant Flip-Flops Across a Wide Supply Voltage Range in a 65 nm Bulk CMOS Process. IEEE Transactions on Nuclear Science.  ISSN 0018-9499.  63(6), s 2962- 2970 . doi: 10.1109/TNS.2016.2614781 Show summary

  In this paper, we investigate the single event upset (SEU) response of five D flip-flops (DFFs) employing temporal redundancy, dual redundancy, and triple modular redundancy (TMR), across a wide supply voltage range. The DFFs were designed and fabricated in a low-power commercial 65 nm bulk CMOS process and were tested using heavy ions with linear energy transfer (LET) between 5:1 MeV-cm2=mg and 99:1 MeV-cm2=mg. Results show an increasing SEU vulnerability with decreasing supply voltage, for most of the DFFs. Nevertheless, radiation tolerant topologies exhibit 14x to 1328x better SEU tolerance than a standard non-radiation tolerant DFF, depending on supply voltage and LET. The general observation is that at normal incidence, while taking the entire LET spectrum into account, the dual interlocked storage cell (DICE) DFF has the best SEU tolerance at supply voltages of 1 V and 0.5 V. At a supply voltage of 0.25 V, a temporal redundant DFF shows the best SEU tolerance, while the TMR DFF shows the best SEU tolerance at a supply voltage of 0.18 V. At supply voltages of 0.5 V and below, increasing the angle of incidence to 45 degrees can increase the SEU rate of the implemented DICE DFF by up to a factor of 22x, making it one of the most SEU sensitive DFFs. Furthermore, utilizing high drive strength components in temporally redundant DFFs can reduce the SEU sensitivity by a factor of 3x to 112x, compared to when standard drive strength components are used.

• Vatanjou, Ali Asghar; Låte, Even; Ytterdal, Trond & Aunet, Snorre (2016). Ultra-Low Voltage Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing, In Ivan Jørgensen & Jens Sparsøe (ed.),  Proceedings of the 2nd IEEE Nordic Circuits and Systems Conference (NORCaS), 2016.  IEEE conference proceedings.  ISBN 978-1-5090-1095-0.  article. Show summary

  Balancing the PMOS/NMOS strength ratio is a key issue to maximize the noise margin, and hence, functional yield of CMOS logic gates in the subthreshold region. In this work, the PMOS/NMOS strength ratio was balanced using a poly-biasing technique in conjunction with back-gate biasing provided in a 28 nm fully depleted silicon on insulator (FDSOI) technology. A 32-bit adder based on minority-3 (min-3) gates and a 16-bit adder based on Boolean gates have been implemented. Chip measurement results show highly energy efficient adders, so that the 32-bit and 16-bit adders achieved minimum energy point (MEP) of 21.5 fJ at 300 mV and 12.62 fJ at 250 mV, respectively. In comparison to adders reported in other works in the same technology, the energy per 1-bit addition of the 32-bit adder is improved by 35% and for the 16-bit adder this improvement in energy consumption is 23%. The designed adders were functional down to a supply voltage of 110 mV. Additionally, the minimum Vdd of the 32-bit adder decreased to 79 mV by applying a reverse back bias voltage to the PMOS devices.

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2016). 28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block, In Andrzej Napieralski (ed.),  Proceedings of the 23rd International Conference - "Mixed Design of Integrated Circuits and Systems" (MIXDES), Lodz, Poland.  IEEE conference proceedings.  ISBN 9788363578084.  kapittel.  s 105 - 110 Show summary

  This paper presents the design of digital logic cells for subthreshold applications using 28 nm ultra-thin body and box fully depleted silicon on insulator technology. The sizing approach relies on balancing pull-up/pull-down networks (PUN/PDN) strength ratio by applying an additional forward back-gate biasing (FBB) voltage to the back-gate of PMOS transistors. The minimum width of PMOS and NMOS transistors have been chosen by taking the narrow width effect into account. Moreover, to increase the functional yield of the logic cells, a trade-off has been made between Ion/Ioff ratio and energy consumption through increasing the channel length by 4 nm. Energy consumption of logic gates analyzed using ring-oscillators consisting of basic logic gates. It has been shown that balancing logic gates through applying an additional FBB to the PMOS back-gate instead of up-sizing PUN results in 30% lower energy consumption in ring-oscillators. An 8-bit multiply-accumulate (MAC) block was synthesized using the fully customized logic cells with asymmetric back-gate biasing. Compared to a state-of-the art MAC, the energy consumption of our MAC was improved by 21% at a relatively high speed (147 MHz).

• Atarzadeh, Hourieh; Aunet, Snorre & Ytterdal, Trond (2015). An Ultra-Low-Power/High-Speed 9-bit Adder Design: Analysis and Comparison Vs. Technology from 130nm-LP to UTBBFD-SOI-28nm, In Jim Tørresen; Snorre Aunet; Tor Sverre Lande; Øyvind Kallevik Grutle & Ivan R. Nielsen (ed.),  Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015.  IEEE conference proceedings.  ISBN 978-1-4673-6576-5.  chapter. Show summary

  A sub-threshold 9-bit adder based on a minority-3 based full adder is designed and analyzed versus technology. A power-delay design space exploration is presented in multiple technology nodes. The performances are demonstrated and compared on spanning technology nodes of 130nm-LP, 65nm-LP-BULK, 28nm-LP-high-k-bulk, 28nm Ultra-Thin-Body-and-BOX (UTFF) FDSOI. An extensive body biasing was then applied to the UTBB FDSOI 28nm technology to adapt the circuit to the target operating frequency of 65MHz. The extensive body biasing exploits the feature provided by the Ultra-Thin-Body-and-BOX Fully Depleted SOI (UTBB FDSOI) technology, which allows a bias range of -300mV/+3V. The design was implemented in physical level, and all the results account for the layout parasitics. A minimum energy point of 1.03fJ/(bit.cycle) is achieved in the 28nm-UTFF-FDSOI, at the 0.24V supply with the 1.8MHz operating speed. For the target frequency of 65MHz and a 9-bit adder, a total minimum energy operation of 11fJ per cycle for a supply voltage of 0.309V and a body voltage of 1.35V is achieved.

• Hasanbegovic, Amir & Aunet, Snorre (2015). Supply Voltage Dependency on the Single Event Upset Susceptibility of Temporal Dual-Feedback Flip-Flops in a 90 nm Bulk CMOS Process. IEEE Transactions on Nuclear Science.  ISSN 0018-9499.  62(4), s 1888- 1897 . doi: 10.1109/TNS.2015.2454479 Show summary

  In this paper we investigate the efficiency of using temporal and spatial hardening techniques in flip-flop design for single event upset (SEU) mitigation at different supply voltages. We present three novel SEU tolerant flip-flop topologies intended for low supply voltage operation. The most SEU tolerant flip-flop among the proposed flip-flop topologies shows ability of achieving maximum SEU cross-section below 1.9 ·10-10 cm2 /bit (no SEUs detected) at 500 mV supply voltage, 4 ·10-10 cm2 /bit at 250 mV supply voltage, and 2 ·10- 9 cm2 /bit at 180 mV supply voltage. When scaling the supply voltage from 1 V down to 500 mV, 250 mV and 180 mV, the proposed flip-flops achieve at least - 72%, - 92.5% and - 95% (respectively) reduction in energy per transition compared to a Dual Interlocked Storage Cell based flip-flop when operated at a supply voltage of 1 V. The flip-flops have been designed and fabricated in a low-power commercial 90-nm bulk CMOS process and were tested using heavy ions with LET between 8.6 MeV-cm2 /mg and 53.7 MeV-cm2 /mg.

• Låte, Even; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28nm FDSOI, In Jim Tørresen; Snorre Aunet; Tor Sverre Lande; Øyvind Kallevik Grutle & Ivan R. Nielsen (ed.),  Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015.  IEEE conference proceedings.  ISBN 978-1-4673-6576-5.  chapter. Show summary

  Nine D flip-flop architectures were implemented in 28nm FDSOI at a target, subthreshold, supply voltage of 200mV. The goal was to identify promising D flip-flops for ultra low power applications. The pass gate flip-flop was implemented using 49% of the S2CFF’s area and was functional at the lowest operating voltage of 65mV in the typical process corner. At the targeted supply voltage of 200mV the racefree DFF gives the best functional yield of 99.8%. The flip-flops having the shortest D-Q delays were the PowerPC 603 and the transmission gate D flip- flop. These also had the lowest power delay products of 52.08aJ and 61.09aJ respectively.

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). 4 Sub-/Near-Threshold Flip-Flops with Application to Frequency Dividers, In Bjørn B. Larsen & Görschwin Fey (ed.),  Proceedings, 2015 European Conference on Circuit Theory and Design.  IEEE conference proceedings.  ISBN 978-1-4799-9877-7.  chapter. Show summary

  Four different flip-flops dimensioned for subthreshold operation have been designed and implemented in layouts. The four full custom, race-free, D-flip-flops were implemented in a standard 65 nm CMOS process and verified by measurements, when used in 2 divide-by-3 circuits. The first frequency divider, using standard topologies, demonstrated functionality down to a supply voltage of 132 mV, while the second variant, based on a recently proposed ”‘slice-based”’ approach, was functional for a supply voltage down to 137 mV. The frequency divider using traditional 4-transistor NAND and NOR topologies had lower energy per operation than the alternative 8-transistor NAND and NOR implementation. At 0.1 MHz, the figures were about 2.1 fJ and 3.5 fJ, respectively. For supply voltages from 0.2 to 1.2 V, a static flip-flop using 8-transistor NOR- gates plus one inverter had the lowest static power consumption among the 4 flip-flops.

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS, In Inon Abdul Hamid; Yiren Chen; Chen-Yong Cher & Ali A. Iranmanesh (ed.),  Proceedings of the 6th Asia Symposium on Quality Electronic Design.  IEEE conference proceedings.  ISBN 978-1-4673-7495-8.  kapittel.  s 7 - 12 Show summary

  This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”), demonstrating functionality for a supply voltage (“Vdd”) down to 84 mV. The low Vdd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32-bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80 nm, respectively. The implementation having 80 nm gate lengths exploits secondary effects like the Reverse Short Channel Effect (“RSCE”) to provide lower energy per operation, compared to the 60 nm implementation, when operated down to subthreshold supply voltages. Dimensioning for symmetric noise margins, and using minority-3 circuits and inverters only, with regular layouts, contribute to the ultra low Vdd potential. According to simulations, the energy per operation could be down to about 1.5 fJ/bit for the implementation, based on L = 80 nm. For delays in the 20 ns to 110 ns range, the energy consumption for the RCA having L = 60 nm, was from 18.5 to 47 % higher than the RCA having L = 80 nm. The area was 9.7 % less for the L = 80 nm implementation, compared to the L = 60 nm RCA. (The manuscript won the best paper award.)

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Exploiting Short Channel Effects and Multi-Vt Technology for Increased Robustness and Reduced Energy Consumption, with Application to a 16-bit Subthreshold Adder Implemented in 65 nm CMOS, In Bjørn B. Larsen & Görschwin Fey (ed.),  Proceedings, 2015 European Conference on Circuit Theory and Design.  IEEE conference proceedings.  ISBN 978-1-4799-9877-7.  chapter. Show summary

  When using standard multi-Vt CMOS processes when making logic gates, often for example Low-Vt (LVT), or Standard-Vt (SVT) or High-Vt (HVT) transistors are used within one and the same basic logic building block, like for example a NAND or NOR circuit. We show, to the contrary, how a combination of different types within a single logic circuit may be exploited to reduce energy consumption and increase robustness towards process variations. Additionaly, Reverse Short Channel Effects (RSCE) are exploited by using non-minimum gate lengths for increased robustness agains process variations. Also, a recently proposed technique using very regular layouts accompanying the above mentioned techniques in a 16-bit adder implemented in 65 nm CMOS. Chip measurements using Sub-/Nearthreshold supply voltages demonstrate the functionality of the adder for a voltage range of 119 mV to 350 mV. Simulations show that by increasing gate lengths to 200 nm instead of the minimum 60 nm, may increase the footprint area of logic gates by only 12%, while at the same time reducing probability of failure by up to several orders of magnitude. Simultaneously, energy per operation is reduced, when compared to conventional design methods using minimum, or relatively short, gate lengths.

• Bjerkedok, Jonathan Edvard; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2014). Modular Layout-friendly Cell Library Design Applied for Subthreshold CMOS, In  Proceedings of the 32nd Norchip Conference.  IEEE conference proceedings.  ISBN 978-1-4799-5442-1.  kapittel.
• Værnes, Magne; Ytterdal, Trond & Aunet, Snorre (2014). Performance comparison of 5 Subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout, In  Proceedings of the 32nd Norchip Conference.  IEEE conference proceedings.  ISBN 978-1-4799-5442-1.  kapittel.
• Berge, Hans Kristian Otnes & Aunet, Snorre (2013). Yield-Oriented Energy and Performance Model for Subthreshold Circuits with Vth Variations, In Lukas Sekanina; Görschwin Fey; Jaan Raik; Snorre Aunet & Richard Růžička (ed.),  Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).  IEEE.  ISBN 978-1-4673-6133-0.  kapittel.  s 193 - 198
• Hasanbegovic, Amir & Aunet, Snorre (2013). Proton Beam Characterization at Oslo Cyclotron Laboratory for Radiation Testing of Electronic Devices, In Lukas Sekanina; Görschwin Fey; Jaan Raik; Snorre Aunet & Richard Růžička (ed.),  Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).  IEEE.  ISBN 978-1-4673-6133-0.  paper.  s 135 - 140
• Lütkemeier, Sven; Jungeblut, Thorsten; Berge, Hans Kristian Otnes; Aunet, Snorre; Porrmann, Mario & Rückert, Ulrich (2013). A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control. IEEE Journal of Solid-State Circuits.  ISSN 0018-9200.  48(1), s 8- 19 . doi: 10.1109/JSSC.2012.2220671 Show summary

  Abstract—An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 sigma/micron), 567 fJ (0.037 sigma/micron ), and 730 kHz (0.184 sigma/micron), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

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• Nurmi, Jari; Wisland, Dag T; Aunet, Snorre & Kjelgård, Kristian Gjertsen (ed.) (2020). Proceedings, Sixth IEEE Nordic Circuits and Systems Conference (NorCAS 2020).. IEEE conference proceedings.  ISBN 978-1-7281-9226-0.  205 s. Show summary

  On behalf of the Organizing Committee, we would like to welcome all of you to the Sixth IEEE Nordic Circuits and Systems Conference (NorCAS 2020). The conference is a merge of the well-established conferences NORCHIP and the International Symposium on System-on-Chip (SoC). We have a high-quality program with keynotes and papers to be presented. Research covering a wide range of topics within circuits and systems in the digital, analog and mixed domains will be presented. From in total 58 papers submitted, 29 papers were selected for oral presentation in the virtual conference, yielding exactly 50% acceptance rate. There will be four invited speakers who will share their view on emerging key technologies in the circuits and systems field. In the opening session Prof. An-Yeu (Andy) Wu from National Taiwan University will discuss compressive sensing and compressive analytics. Later in the afternoon Prof. Alberto Bosio from ICL, France, will give insights to approximate computing and, in particular, testing of it. In the second morning, Prof. Tim Constandinou from University College London, UK, will present his talk on “Future Human: Merging Minds and Machines.“ The final talk is given by Prof. Alexander Wyglinsky from Worchester Polytechnic Institute, USA, introducing an educational view to Software-Defined Radio. We would like to forward great thanks to IEEE Circuits and Systems Society (CAS) for financial co-sponsoring of the conference. Thanks also to Tampere University and University of Oslo for the efforts on the congress office and virtual platform. We are also thankful to all the Program Committee members and reviewers who have put time and effort into reviewing the submitted papers. Moreover, we are grateful to the NorCAS steering committee for helpful advice and their contribution in the paper selection process. We hope that you will enjoy your time in the virtual conference. We wish you an inspiring conference where your knowledge is increased and friendships are both established and strengthened.

• Tørresen, Jim; Aunet, Snorre; Lande, Tor Sverre; Grutle, Øyvind Kallevik & Nielsen, Ivan R. (ed.) (2015). Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015. IEEE conference proceedings.  ISBN 978-1-4673-6576-5.  275 s.
• Sekanina, Lukas; Fey, Görschwin; Raik, Jaan; Aunet, Snorre & Růžička, Richard (ed.) (2013). Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE.  ISBN 978-1-4673-6133-0.  320 s.

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• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). 0 Comparative Study of Single, Regular and Flip well Subthreshold SRAMs in 22 nm FDSOI Technology.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). 0 Multi-threshold voltage and dynamic body biasing techniques for energy efficient ultra low voltage subthreshold adders.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). An ultra low voltage subthreshold standard cell based memories for IoT applications.
• Aunet, Snorre (2019). Asynchronous ultra low voltage / low power CMOS - what and why, but not much about how.. Show summary

  Reducing the supply voltage to the subthreshold region, where the supply voltage is below the absolute values of the inherent threshold voltages, has been regarded the most direct and dramatic means of reducing overall power consumption. Full Custom logic and memory building blocks are needed to take full advantage of subthreshold operation, that may reduce power consumption by orders of magnitude, and energy per operation by typically 10 times or more, compared to normal super-threshold circuits. The lower the supply voltage, the lower the power consumption. Examples of a 32-bit RISC processor operating at subthreshold voltages, as well as arithmetic building blocks operating at supply voltages below 100 mV are mentioned briefly. The strong relationships between supply voltage and power consumption, as well as energy per operation, are due to several exponential relationships between voltages across nodes of the transistor, temperature and threshold voltages, in subthreshold operation. Dealing with process-, voltage-, and temperature (“PVT”-) variations is the greatest challenge when exploiting subthreshold techniques for ultra low power / low energy circuits. Circuit delays can vary by up to orders of magnitude, due to PVT variations. When the traditional synchronous circuits design paradigm is used, combined with subthreshold operation, necessary worst-case timing considerations leads to slowing down circuitry by up to orders of magntitude, while at the same time increasing power- and energy consumption radically, compared to superthreshold / strong inversion circuits. To fully exploit the low power / low energy potential of subthreshold circuits, asynchronous solutions not taking worst case behavior into account in the normal fashion, may be a key concept.

• Boland, Connor; Aunet, Snorre & Moldsvor, Øystein (2019). Low Power Environmental Air Quality Monitoring. Show summary

  Measuring personal environmental air quality is becoming increasingly relevant in today's society. Traditional monitoring requires oversized, expensive instruments, with slow and intensive sampling methodologies. Scalable, low-cost monitors are required to replace these outdated designs, to increase global access to air quality data. Disruptive Technologies provides long lifetime IoT solutions, specialising in smart wireless sensors. The aim of this project is therefore to develop a battery-operated environmental air quality monitor, with lifetime standards in line with those at Disruptive Technologies. The monitor must not only be able to measure a number of harmful air contaminants but also to measure the quality of the working environment. Specific emphasis on particulate matter sensing will provide a monitor with commercial viability. A number of particulate matter sensors were introduced. Initial current measurements on each were conducted to test their individual feasibility as part of a complete battery-powered monitor. Out of all of the tested sensors, only the Sharp GP2Y10AU0F compact optical dust sensor showed low current consumption for battery operation. A number of techniques to reduce this power consumption were introduced as part of a test design with the Sharp sensor and a microcontroller. Overall the calculated energy requirement for the sensor came to 1 638J for a two year lifetime. This was combined with two other sensors (one sensor measuring both volatile organic chemicals (VOC) and carbon dioxide (CO2), and the other sensor measuring both temperature and humidity) as a model of the complete energy requirements for the monitor. The total calculated energy consumption came to 125 968J, far exceeding a standard battery capacity of up to 39 960J. The unforeseen power limitation of this design was with the chosen VOC sensor, however, the project has still shown feasible opportunities for a battery powered environmental air quality monitor capable of measuring particulate matter.

• Christensen, Steinar Thune; Aunet, Snorre & Qadir, Omer (2019). En Konfigurerbar og Fleksibel Arkitektur for Laveffekt, Energieffektiv Maskinvareakselerasjon av Nevrale Nettverk basert på Foldning. Show summary

  Convolutional neural networks (CNNs) have become paramount in today’s Artificial Intelligence (AI) and Machine Learning applications. This is true for image recognition in particular. This thesis presents a configurable, versatile and flexible architecture for hardware acceleration of CNNs that is based on storing and accumulating the entire feature maps in local memory inside the accelerator. This has been done while aiming to be able to process any type of CNN while consuming as low power as possible and achieving the highest possible energy efficiency, which refers to the number of operations per unit energy (measured in Multiply-Accumulate operations per unit energy, MACs/s/W or MACs/J). Several different versions of the architecture have been synthesized and tested using different configurations. It performs well when compared to the state-of-the-art, achieving an improved energy efficiency of over a factor 5 for select CNN layers. The most efficient configuration achieves 175 GMACs/s/W, while consuming 2.3 mW of power and occupying 585 KGEs (Kilo Gate Equivalents) of area at 1V supply voltage and a 100MHz clock. This is a significant improvement over Eyeriss [YuH17b] (a state-of-the-art accelerator) which has a maximal energy efficiency of 122.8 GMACs/s/W.

• Fini, Simone; Ytterdal, Trond; Aunet, Snorre & Lavagno, Luciano (2019). Sub-Threshold Design of Arithmetic Circuits: when Serial might overcome Parallel Architectures. Show summary

  Adder circuits are vital for microprocessors; indeed, apart from the addition itself, either subtraction, multiplication or division algorithms may require, at a certain point, the addition of two (partial or not) operands. For this reason, several architectures have been studied and improved over the last decades, in order to speed up the aforementioned operation. On the other hand, it is well known that having faster circuits means higher complexity, and, therefore, higher power consumption. In addition to this, the downscaling process of transistors has increased the leakage current of these devices, accounting for up to 33% of the total dissipation, and due to the little capabilities of batteries with respect to the achievable performance of circuits, the main challenge of engineers and designers is represented by exploiting low power techniques so as to decrease the power consumption of electronic devices as much as possible. This Master’s Thesis work wants to demonstrate that, when working in sub-threshold region, it might be possible to employ simple and repetitive circuits, like ripple carry adders, instead of complex ones, such as Kogge-Stone architectures, having the same propagation time but with a significantly lower energy consumption. In this way, it would be possible to have, at the same time, the performance given by a fast adder and the area and energy dissipation of the simpler and weaker "anchestor". As an anticipation, and as it will be seen in the final results, the technology employed and the choice of the best available architecture resulted in a great improvement with respect to the study previously conducted. First of all, with the development of a new full adder circuit (the so called "XMAJ3"), it is possible to reduce the energy consumption with respect to ripple carry adders based on both already existing architectures and on the full adder cell contained in the library. This even without the employment of customized gates, but only with standard logic blocks already contained in the library. Secondly, FDSOI technology makes possible to equalize performance of serial and parallel adders and, at the same time, saving energy, even in super-threshold region, allowing to avoid all the problems that subthreshold design brings. Particularly, for 32-bit based devices, the average energy saving with respect to the Kogge-Stone adder accounts for 41.48% (with a peak of 56.16%), while for 64-bit adders the mean saving is 50.02%, with a maximum of 56.83%.

• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2019). Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology.
• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2019). Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder.
• Paintsil, Wesley Ryan; Aunet, Snorre & Moldsvor, Øystein (2019). A comparative study for commercial TVOC sensors. Show summary

  Indoor air quality has become more important as human activity is increasingly spent inside. Internet of things has allowed for humans to better interact with the physical world by extracting information through sensor nodes. Indoor air quality sensors of different types have become increasingly popular, this thesis focuses on total volatile organic compound sensors. Three different sensors have been chosen and their operations evaluated by their power consumption. The Bosch BME680 proved to be the best sensor in terms of low-power, it had a lifetime of 4847 days as an alarm system and a lifetime of 2403 days if it acted as a monitoring system. The Integrated Devices Technologies ZMOD4410 only had a lifetime of 8 days. The AMS CCS811 had a lifetime of 871 days as an alarm system and 191 as a monitoring system. The BME680 had an integrated humidity and temperature sensor which provided an advantage by letting the host controller sleep longer. It should be possible to drive the BME680 and the CCS811 sensor with a 230mAh battery for more than 2 years.

• Seyedi, Azam; Aunet, Snorre & Kjeldsberg, Per Gunnar (2019). Towards Compact Radiation Hardened Memories for Space Applications.
• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2019). Ultra Low-Power/Low-Energy CMOS Mixed-Signal Building Blocks.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2019). Ultra low voltage subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2019). Low Energy CMOS building blocks for IoT.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2019). Low Energy CMOS building blocks for IoT.
• Aunet, Snorre (2018). Possibilities with ultra low power / low energy integrated circuits.
• Choe, Ju Song; Gheorghe, Codin & Aunet, Snorre (2018). Test system design for a Photomultiplier Readout Board. Show summary

  The S-DAM front-end board (S-DAM-FEB) is a photomultiplier readout module for charged particles detection. This board has been designed for the readout of sensors in radiation monitors by the company, Integrated Detector Electronics AS (IDEAS). A large amount of S-DAM-FEB will be used in the neutron detector in the ESS (European Spallation Source) in Sweden for scientific research. Thus, hundreds of these modules are planned to be manufactured by third party of EMS (Electronic Manufacturing Service) and each board has to be validated after production. To be able to validate the DUTs efficiently, it has been decided to create a test system. In this thesis, the main focus was on the implementation of the test system to validate the functionality of the S-DAM-FEB. The project work included specifying the test requirements, conceptualization of the test system, schematic design and PCB design of needed hardware as well as implementing firmware and software for the test system. The needed Python scripts were created to run the test and log the test results into a test report. The mechanics of the test system was modelled by drawing a 3D-model, and the mechanical components were chosen according to the drawings. After implementing all the modules to be used for the test system, these modules were assembled together. The S-DAM-FEB was tested using the implemented test system. All functionality of the DUT was tested, including power consumption and temperature as well as gain, threshold and baseline for all channels. Minor fault in the DUT were found by the test, indicating that some failure has occurred during the production process. All the test results were logged into a test report for tracking the modules for future use and determine the condition of DUTs after production. The test system is in a working condition. Performing the validation test simple and easy. The runtime of the test is decreased, and most of the manual work is replaced by automatized process to get more reliable data and minimize possible human errors. The implementation of the test system was successful, and a large amount of S-DAM-FEB are ready to be validated.

• Paldas, Auritro; Barzic, Ronan & Aunet, Snorre (2018). Towards Predictable Placement of Standard Cells for Regularly Structured Designs. Show summary

  A lot of components in modern digital designs have very regular structures. Some examples are Programmable Ring Oscillators, Time to Digital Converters and CPU register files. The proper functioning of these components heavily depend on the way they are implemented in the design with respect to the placement of standard cells. This is due to the fact that many of these components are delay sensitive and the placement of cells in the layout affects the delay. Standard place and route tools, however, do not always ensure that the placement of standard cells is regularised, which can lead to sub-optimal results from these designs. The work on this thesis is aimed towards ensuring a regular placement of standard cells for such components, by developing a framework in a high-level language, from which the placement information needed by the place and route tools can be obtained. This information, when used by the tool, should result in a more predictable placement of standard cells, and should thus result in more optimal behaviour of such components.

• Rørstad Helle, Even; Moldsvor, Øystein; Hernes, Bjørnar & Aunet, Snorre (2018). Humidity Sensor.
• Stubsjøen, Sivert; Moldsvor, Øystein & Aunet, Snorre (2018). Force measurement using a capacitive sensor and a compressible material. Show summary

  Disruptive Technologies are developing sensor solutions for the Internet of Things. Their current sensors can measure touch, temperature, and proximity. To expand the area of applications their current sensors cover, new sensor solutions are examined. The one studied in this thesis is a capacitive sensor measuring force. The idea is to place a compressible material on the front of Disruptive Technologies capacitive proximity sensor and use it to measure force. A compression of the material would lead to an increased capacitance measured. This thesis covers the work of finding suitable materials and the practical measurements done to characterize the capacitive sensor and the compressible material. Testing was done at two different materials that had properties useful for the intended application. These tests revealed that neither of the materials was optimal for a solution as described above. For different series of measurements, the values measured by the sensor variated for the same applied load. This made the work of creating a good fitting data model difficult. The proposed models could not predict with high probability the values measured by the sensor for the various applied loads. This lead to the conclusion that either the materials or the chosen sensor solution was not the optimal one for measuring force. As a result of this, two other force sensing methods using the same sensor is presented that can be further investigated in future work.

• Østerhus, Stian; Ytterdal, Trond & Aunet, Snorre (2018). Subthreshold CMOS Cell Library by 22 nm FDSOI Technology. Show summary

  Two different CMOS transistors with a low threshold voltage, given by a commercial available 22 nm FDSOI CMOS technology were investigated and assembled into several libraries of logic gates. The logic gates provided in the cell library should be sufficient to create most digital logic circuits, and are in addition designed to work in the subthreshold region with a supply voltage of 350 mV. Physical layout designs were made for the different digital ports, where parasitic capacitances were then extracted to provide more realistic simulations and performance results. Compared to schematic simulation, layout design and parasitic capacitances proved to reduce speed by a factor of 5 to 10, as well as increasing the transistors’ threshold voltage by 14.6 % for the NMOS, and 32.5 % for the PMOS. The increased threshold voltage thus led to a reduced static power consumption and increased switching energy. The transistor with the lowest threshold voltage showed especially good performance results with respect to low power consumption while still maintaining speed requirements. This transistor is throughout the report referred to as mosfet low. Two cell libraries were made for this transistor, where one applies a forward body-bias of ±2 V while the other have the bulk nodes connected to ground, which gives a 0 V body-bias. The libraries are supplied with schematics and layout designs, and are in addition mapped for performance data such as static power consumption, delay and switching energy consumption for every logic gate. A minimum speed of 40 MHz with a lowest possible power consumption for a 16by12-bit adder, was the aim of the project. Presented in this report is a 16by12-bit Adder built by Ripple-Carry Adders, which were simulated to reach a speed of 44.26 MHz at a supply voltage of VDD=350 mV with 0 V body-bias. Static power and switching energy consumption were simulated to 26.60 µW and 207.95 fJ, respectively.

• Aunet, Snorre (2017). Introduction to ultra-low power electronic circuits design.
• Aunet, Snorre (2017). Introduction to ultra-low power electronic circuits design.
• Aunet, Snorre (2017). Introduction to ultra-low power electronic circuits design.
• Aunet, Snorre (2017). Ultra-low power electronic circuits for medical applications.
• Hasanbegovic, Amir; Siem, Sunniva; Søråsen, Oddvar & Aunet, Snorre (2017). Exploring the SEU Dependence on Supply Voltage scaling in 90 nm and 65 nm CMOS Flip-flops. Full text in Research Archive.
• L'Orange, Simon; Hagen, Anders; Blekken, Brage; Ytterdal, Trond & Aunet, Snorre (2017). 4-7Ghz Tunable Programmable Pulse Generator in 65nm CMOS.
• Lesund, Martin; Tjora, Sigve & Aunet, Snorre (2017). Ultra-low power serial communication for Internet of Things.
• Lid, Gunnar; Hagen, Anders; Blekken, Brage; Ytterdal, Trond & Aunet, Snorre (2017). Ultra-low power Design of DSRC modulator/demodulator in 28nm FD_SOI.
• Tørresen, Jim & Aunet, Snorre (2017). Special issue: Selected papers from the 1st NORCAS conference (2015 Nordic Circuits and Systems Conference (NORCAS): Norchip & International Symposium on System-on-Chip (SoC)). Microprocessors and microsystems.  ISSN 0141-9331.  48, s 1- 2 . doi: 10.1016/j.micpro.2016.11.008
• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2017). Ultra-Low Voltage/Energy CMOS Building Blocks in 28 nm FDSOI Technology.
• Aunet, Snorre & Tørresen, Jim (2016). Special issue: selected papers from the 1st NORCAS conference (2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium on System-on-Chip (SoC)). Analog Integrated Circuits and Signal Processing.  ISSN 0925-1030.  89(2), s 271- 272 . doi: 10.1007/s10470-016-0847-5
• Barua, Anomadarshi; Edwin, David & Aunet, Snorre (2016). Voice over mesh network.
• Kvam Oma, Åsmund; Låte, Even; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2016). Design of a near-threshold microcontroller. Show summary

  There is a strong interest in ultra low voltage digital design as emerging applications like Internet of Things, wearable biomedical sensors, radio frequency identification, sensor networks and more are gaining traction. This thesis describes the implementation, synthesis and testing of a microcontroller using a near-threshold library. The system has been described in VHDL and synthesized for near-threshold operation on 28 nm FDSOI production technology from STmicroelectronics. The microcontroller implements a 32 bit RISC-V subset compatible pipelined processor and has SPI connectivity. Two single port 2kB SRAM modules are used as RAM. A power gating technique that reduces the static power in an ALU during runtime has been implemented and compared to a traditional ALU. Traditional coarse grain power gating of the processor has also been implemented. Using a supply voltage of 350 mV and a clock speed of 1 MHz the schematic SPICE simulation reported an average power consumption of 4.42 mW during program execution. In power gated mode the microcontroller consumed 2.98 mW. In a sensor logging program the average energy per executed instruction was 4.91 pJ. Runtime power gating reduced the average energy consumption of the ALU with 58 - 57% with a propagation delay penalty of 346 - 143% depending of the sizing of the power gating transistors.

• Liknes, Kai Robert; Hernes, Bjørnar & Aunet, Snorre (2016). Ultra Low Leakage Memory. Show summary

  Three 64-byte memory systems were designed for a 0.18µm standard CMOS technology, one 6T-SRAM system and two D-Flip-Flop systems. The leakage current, read energy and write energy of these systems were determined by simulation. A set of extrapolation formulas for area, leakage current, read energy and write energy were designed to determine the characteristics of the systems as the size of the memory increases. The simulations showed that the 64-Byte 6T-SRAM system had a 39% lower area, an 83% lower leakage current, an 89% lower write energy and an 82% lower read energy than the reference D-Flip-Flop memory system. The extrapolation formulas predicted that as memory sizes increases, SRAM becomes more and more favorable in terms of area, leakage current, write energy and read energy.

• Vatanjou, Ali Asghar; Låte, Even; Ytterdal, Trond & Aunet, Snorre (2016). Ultra-Low Voltage Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing.
• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2016). 28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block.
• Atarzadeh, Hourieh; Aunet, Snorre & Ytterdal, Trond (2015). An Ultra-Low-Power/High-Speed 9-bit Adder Design: Analysis and Comparison Vs. Technology from 130nm-LP to UTBBFD-SOI-28nm.
• Aunet, Snorre (2015). Ultra Low Power / Low Energy Integrated Circuits.
• Aunet, Snorre (2015). Ultra Low-Voltage / Low energy circuits.
• By, Mathias; Kile, Eirik & Aunet, Snorre (2015). FPGA Implementation and Evaluation of a Genetic Algorithm for Digital Adaptive Nulling using Space-Time Adaptive Processing.. Show summary

  The thesis is done in cooperation with Kongsberg Defence Systems.

• Hals, Erik; Aunet, Snorre; Ramstad, Tor Audun; Hagen, Anders & Blekken, Brage (2015). Lav effekt sensornettverk, for registrering av kjøretøy.
• Holen, Aslak Lykre; Ytterdal, Trond & Aunet, Snorre (2015). Implementation and Comparison of Digital Arithmetics for Low Voltage / Low Energy Operation.
• Låte, Even; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28nm FDSOI. Show summary

  Nine D flip-flop architectures were implemented in 28nm FDSOI at a target, subthreshold, supply voltage of 200mV. The goal was to identify promising D flip-flops for ultra low power applications. The pass gate flip-flop was implemented using 49% of the S2CFF's area and was functional at the lowest operating voltage of 65mV in the typical process corner. At the targeted supply voltage of 200mV the racefree DFF gives the best functional yield of 99.8%. The flip-flops having the shortest D-Q delays were the PowerPC 603 and the transmission gate D flip-flop. These also had the lowest power delay products of 52.08aJ and 61.09aJ respectively.

• Pedersen, Arne Olav Gurvin; Gheorghe, Codin & Aunet, Snorre (2015). Design of an ASIC Evaluation Kit - Conceptualization, schematic design, PCB layout and preliminary testing of a mixed-signal board. Show summary

  The development of an upcoming ASIC by the company IDEAS calls for the design of an accompanying evaluation kit so that it may be accessible for testing in a laboratory setting. In addition to supporting the ASIC in question, the kit was decided to be made general purpose, leading to the support of various other ASICs from IDEAS, both future and existing ones. This thesis focuses on the creation of the primary board in the evaluation kit, named the Galao board. The project work included conceptualization, schematic design and PCB design of the Galao board, as well as producing relevant documentation for IDEAS. Being a mixed-signal general purpose board, effort has been made to include a high number of features and connectivity options: Galao holds specialized analog circuits for receiving differential signals, transmitting fast pulses of adjustable amplitude, registering trigger signals for readout synchronization as well as containing a broad assortment of both voltage and current bias generators. On the digital side, a System on Module solution has been incorporated, serving as a control unit for all the analog circuitry while providing a large amount of digital I/Os. The board has been made so that it may be accessed through Ethernet, USB and JTAG interfaces. Furthermore, the Galao board has several power rails, both for the analog and digital domain, with the PCB designed so that digital switching has a minimal impact the analog signals. The Galao board was finally produced, allowing for some initial testing. The results of the conducted tests are positive, as the board powers up and is operational with its digital logic being fully controllable. Some faults in the schematic have been discovered after the manufacturing of the Galao board, but these have all been readily fixable. The board is hence in a working condition, and ready to be interfaced towards an ASIC with an ASIC test board that is to be designed.

• Skjølsvik, Hallstein; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Ultra low voltage combinatorial logic building blocks.
• Talstad, Joar Nikolai; Diaz, Isael; Øye, Jan Egil & Aunet, Snorre (2015). Channel Filter Cross-Layer Optimization.
• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). 4 Sub-/Near-Threshold Flip-Flops with Application to Frequency Dividers. Show summary

  Four different flip-flops dimensioned for subthreshold operation have been designed and implemented in layouts. The four full custom, race-free, D-flip-flops were implemented in a standard 65 nm CMOS process and verified by measurements, when used in 2 divide-by-3 circuits. The first frequency divider, using standard topologies, demonstrated functionality down to a supply voltage of 132 mV, while the second variant, based on a recently proposed ”‘slice-based”’ approach, was functional for a supply voltage down to 137 mV. The frequency divider using traditional 4-transistor NAND and NOR topologies had lower energy per operation than the alternative 8-transistor NAND and NOR implementation. At 0.1 MHz, the figures were about 2.1 fJ and 3.5 fJ, respectively. For supply voltages from 0.2 to 1.2 V, a static flip-flop using 8-transistor NOR- gates plus one inverter had the lowest static power consumption among the 4 flip-flops.

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS. Show summary

  This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (”RCA”), demonstrating functionality for a supply voltage ("Vdd") down to 84 mV. The low Vdd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32- bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80 nm, respectively. The implementation having 80 nm gate lengths exploits secondary effects like the Reverse Short Channel Effect (”RSCE”) to provide lower energy per operation, compared to the 60 nm implementation, when operated down to subthreshold supply voltages. Dimensioning for symmetric noise margins, and using minority-3 circuits and inverters only, with regular layouts, contribute to the ultra low Vdd potential. According to simulations, the energy per operation could be down to about 1.5 fJ/bit for the implementation, based on L = 80 nm. For delays in the 20 ns to 110 ns range, the energy consumption for the RCA having L = 60 nm, was from 18.5 to 47 % higher than the RCA having L = 80 nm. The area was 9.7 % less for the L = 80 nm implementation, compared to the L = 60 nm RCA.

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Exploiting Short Channel Effects and Multi-Vt Technology for Increased Robustness and Reduced Energy Consumption, with application to a 16-bit Subthreshold Adder Implemented in 65 nm CMOS. Show summary

  When using standard multi-Vt CMOS processes when making logic gates, often for example Low-Vt (LVT), or Standard-Vt (SVT) or High-Vt (HVT) transistors are used within one and the same basic logic building block, like for example a NAND or NOR circuit. We show, to the contrary, how a combination of different types within a single logic circuit may be exploited to reduce energy consumption and increase robustness towards process variations. Additionaly, Reverse Short Channel Effects (RSCE) are exploited by using non-minimum gate lengths for increased robustness agains process variations. Also, a recently proposed technique using very regular layouts accompanying the above mentioned techniques in a 16-bit adder implemented in 65 nm CMOS. Chip measurements using Sub-/Nearthreshold supply voltages demonstrate the functionality of the adder for a voltage range of 119 mV to 350 mV. Simulations show that by increasing gate lengths to 200 nm instead of the minimum 60 nm, may increase the footprint area of logic gates by only 12%, while at the same time reducing probability of failure by up to several orders of magnitude. Simultaneously, energy per operation is reduced, when compared to conventional design methods using minimum, or relatively short, gate lengths

• Zapatero, Miguel & Aunet, Snorre (2015). Synthesis of low-energy near-threshold SHMAC processor core.
• Benemann, Danton Canut; Milch Pedersen, Frode & Aunet, Snorre (2014). Ultra-low voltage embedded processor system for Internet-of-Things microcontrollers.
• Bjerkedok, Jonathan Edvard; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2014). Modular Layout-friendly Cell Library Design Applied for Subthreshold CMOS.
• Dybwad, Patrick; Hasanbegovic, Amir & Aunet, Snorre (2014). Automated Single Event Transient simulation program using high-level programming.
• Green, Allan; Barzic, Ronan & Aunet, Snorre (2014). Ultra-low Power Stack-based Processor for Energy Harvesting Systems. Show summary

  The work is done in cooperation with Atmel Norway, with Ronan Barzic as advisor at Atmel. Summary: The fast evolution of the Internet of Things suggests an unavoidable transition to this infrastructure in the near future, and to achieve this multiple nodes need to interconnect and communicate efficiently. All nodes will need a power source to operate. Most of them will have very low power consumption requirements. Therefore, a possible solution would be to have an energy harvesting system for the nodes. The energy harvesting systems will need a CPU to control all operations and to manage the power consumption. The goal of this assignment is to create a base processor capable of controlling the system using ultra-low levels of power. The proposed approach for the assignment is to use a stack processor. Using the J1 processor as a reference, a new architecture was designed. The design process was done following the design flow tools used by Atmel and covered the simulation, testing, synthesis and place and route process. The end result of the assignment was a functional stack processor system with the capability to communicate with I/O modules using a Wishbone bus. A custom assembler was created using Arch C to simplify the testing of the architecture. The design was simulated, synthesized and routed using specific libraries from Atmel. The assignment completed a working design flow that will allow the realization of a proper power analysis in the next phase of development. The stack processor architecture shows high potential for ultra-low power operations. Further time and power analysis is needed to have a complete comparison with other processors.

• Johnsen, Glenn Andre; Herheim, Jan Rune & Aunet, Snorre (2014). Full-Custom Sub-/Near-Threshold Cell Library in 130nm CMOS with Application to an ALU. Show summary

  The work was done in coopertion with Atmel Norway (www.atmel.com). Summary: This thesis presents a cell library with limited functionality targeting to operate in sub-threshold (350mV) as well as above-threshold (1.2V) voltages utilizing the dynamic speed requirement of the circuit. The sub-threshold cell library can be used to synthesize any general Finite State Machine (FSM) since it contains logic gates and a D-FF memory element. The sub-threshold cell library proposed in this thesis consists of: Inverter, NAND2, NOR2, XNOR2, XOR2, AOI22, OAI22 and D flip-flop. All cells are designed with static CMOS and use of 130 nm HVT n-well process. The main motivation behind this work is the desirable for longer lasting battery powered IC chips. CMOS power consumption includes three components where the dynamic component is Pdyn ∝ V 2 DD . Hence, a promising method to reduce power consumption is to reduce the supply voltage V DD to the sub-threshold region. The reduction of V DD increases the delay through the circuit (excellent trade-off in application with low performance requirements) and increases sensitivity to process, voltage and temperature (PVT) variations. The sub-threshold cells are evaluated with an ALU synthesized into three circuits: No.1: unlimited, with use of provided above-threshold cells; No.2: limited to INV, NAND2, NOR2 and D-FF with sub- and above-threshold cell library; and No.3: limited as No.2 + XNOR2, XOR2, AOI22 and OAI22 with sub- and above-threshold cell library. The results shows a power consumption reduction of ∼ 14 times from V DD = 1.2V to 350mV for both No.2 and No.3 ALU circuit. It is also shown that a more complex library including XNOR2, XOR2, AOI22 and OAI22 reduces the power consumption with ∼ 7.7% compared to a library with only Inverter, NAND2, NOR2 and D-FF at 350mV. The No.3 circuit is shown to be the best ALU with use of sub-threshold cells in term of delay and power consumption. Both No.2 and No.3 only fails to comply with the 32KHz frequency in SS and FS corner in −40 ◦ C , 350mV and with use of sub-threshold cells, whereas with use of above-threshold cells fails in all except FF corner in −40 ◦ C , in addition to failing in SS corner at 25 ◦ C .

• Låte, Even; Schanche, Morten; Bugge, Håkon & Aunet, Snorre (2014). Transaction Level Modeling of a PCI Express Root Complex. Show summary

  The work was done in cooperation with Oracle, Oslo, Norway. Summary: PCI Express(PCIe) is a packet-based, serial, interconnect standard that is widely deployed within servers and workstations for it’s attractive performance capabilities. A platform that has a PCIe architecture also includes a PCIe Root Complex(RC) for linking the PCIe device-tree to the host CPU and memory. During the design-phase of a PCIe endpoint-device it is highly desired to conduct computer aided simulations of the device in a relevant environment. Having a simulation software that can be applied early and iteratively in the design-phase enables engineers to tweak the product without realization of hardware. Causing a great reduction in the number of physical prototypes required before mass production. In this thesis a transaction level model(TLM) of a PCIe RC was assembled using SystemC, with a focus on latency and jitter as performance parameters. The model gives the Application Specific Integrated Circuit(ASIC) developers at Oracle a timing accurate alternative to the existing processor emulator(QEMU) that is used for the same purpose. To correlate the RC TLM with real hardware, a PCIe protocol analyzer from LeCroy was utilized. Traffic between a first generation PCIe endpoint-device and a SUN FIRE X4170 M3 server was traced. The RC TLM was made in a modular manner allowing support for other micro-architectures through insertions of trace files. The recorded traces between requests and completions were processed and inserted directly into a delay database within the RC model, to ensure high correlation between the RC TLM and the real hardware. A simple model of a PCIe endpoint-device was implemented to serve as a suitable test-environment. The functionality and the hardware realisticness of the RC model was successfully tested with targeted transaction scenarios. A simulated latency distribution of 15000 packets, proved to fit the latency distribution that was randomly drawn in the RC TLM. Only a small amount of negligible delay anomalies from imperative switch cycles were found. The PCIe RC TLM is close to optimal for modeling latency and jitter using a database of targeted trace calbrations. The principle of modeling delays in an RC TLM using latency databases, was found to be a favorable alternative to the constant delay nature of the QEMU test-environment. The master thesis won the award for the best thesis within microelectronics, at NTNU, 2014.

• Myrvang Ro, Hans Jørgen; Øye, Jan Egil & Aunet, Snorre (2014). Analysis and Visualisation of Clock Three power in a full-chip-design. Show summary

  Oppgaven er båndlagt. / The thesis will not be public until 3 years from now (some time in 2017).

• Samstad Kjøbli, Ole; Aunet, Snorre & Herheim, Jan Rune (2014). Ultra-Low Voltage SRAM in 130 nm CMOS Process. Show summary

  Energy harvesting systems typically contain a low-power embedded processor in order to collect and interpret sensory data and such a processor will need memory to store that data. The most effective method of reducing power consumption in an electronic circuit is to decrease the supply voltage and this thesis explores the viability of implementing an ultra-low voltage SRAM architecture in a 130nm CMOS process for Atmel Norway AS. The architecture supports voltage scaling between 400mV and a regular supply voltage of 1.2V. The architecture was implemented with conventional 6T SRAM cells and 10T SRAM cells designed for low-voltage operations using state of the art design techniques and literature. The SRAM architecture is asynchronous and self-timed to more easily cope with the effects of process and temperature variations. To realize the architecture a small set of logic gates were also designed for ultra-low voltage operation and used in the SRAM read and write control circuitry. All building blocks in the architecture were simulated with extracted parasitics to get more realistic simulation results. Corner and Monte Carlo simulations were used to show how temperature and process variations statistically affected the building blocks and their performance. Simulation results showed that the 10T SRAM cell is more robust with a 60-100% larger static noise margin compared to the conventional 6T cell, but draws 1.2-1.6 times more leakage power and is physically 64% larger. The differential nature of the 6T cell makes its read operations faster compared to the 10T cell, but the offset voltage in the sense amplifiers used for reading reduces the potential speed gain somewhat. The 6T cell also experience a disturb voltage during read operations and the nature of this disturbance is different at subthreshold and superthreshold voltages, making it difficult to assess yield in a system supporting voltage scaling. the 10T cell does not experience this problem which makes it the more predictable and safe choice for future implementations. Reducing the voltage from 1.2V to 400mV gives a power saving in the range 4-18 depending on process variations and temperature. At low temperatures the supply voltage must be increased either permanently or by using dynamic voltage compensation to perform a read operation within a 32kHz clock cycle. This thesis has showed that it is viable to implement a subthreshold SRAM architecture in the Atmel 130nm CMOS process and some important effects of applying voltage scaling have been explored. Reducing the power supply to such an extent reduces performance and will need some form of voltage compensation to increase performance at low temperatures.

• Værnes, Magne; Ytterdal, Trond & Aunet, Snorre (2014). Performance comparison of 5 Subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout.
• Aunet, Snorre (2013). Low Voltage / Low Energy CMOS.
• Aunet, Snorre (2013). Ultra low voltage CMOS reducing power consumption up to several orders of magnitude, or energy per switching up to 1-2 orders of magnitude.
• Bjerkedok, Jonathan Edvard; Aunet, Snorre; Grannæs, Marius & Ekelund, Øivind (2013). Subthreshold Real-Time Counter.
• Myhre, Petter; Pihl, Johnny & Aunet, Snorre (2013). A novel 55 nm Path Delay Monitor - saving power with DVFS.
• Schjolden, Lars-Frode; Aunet, Snorre & Ytterdal, Trond (2013). Low Energy Implementation of Robust Digital Arithmetic in Sub/Near-Threshold Nanoscale CMOS - for ultrasound beamforming.
• Taugland Kollerud, Martin; Pihl, Johnny & Aunet, Snorre (2013). Extended Bubble Razor Methodology and its Application to Dynamic Voltage Frequency Scaling Systems.
• Værnes, Magne; Aunet, Snorre & Hagen, Anders (2013). Trade-offs between Performance and Robustness for Ultra Low Power/Low Energy Subthreshold D flip-flops in 65nm CMOS.
• Halvorsen, Are; Røkenes Myren, Sindre; Hopland Sperre, Andreas; Hendseth, Sverre & Aunet, Snorre (2012). Eurobot NTNU 2012 - Treasure Island. Show summary

  eurobot er en årlig internasjonal konferanse for autonome roboter. Gruppen har utviklet en komplett, fungerende robot, med gode mekaniske løsninger. Det utviklede styresystemet tillater hurtig re-programmering av strategier, selv like før en kamp. posisjoneringssystemet kan frakte roboten til en hvilken som helst koordinat på spillebrettet. Roboten vant fem kamper i Eurobot 2012, noe som resulterte i en 23. plass blant 43 internasjonale lag.

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