Snorre Aunet

• Seyedi, Azam; Aunet, Snorre & Kjeldsberg, Per Gunnar (2022). Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications with High Reliability Requirements. IEEE Access. ISSN 2169-3536. 10, p. 30624–30642. doi: 10.1109/ACCESS.2022.3157402.
• Su, Shengkai; Truong, Binh Duc; Aunet, Snorre & Le, Phu Cuong (2021). A reliable and wide-range tuning technique for low-frequency MEMS energy harvesters. In Jia, Yu (Eds.), Proceedings, 2021 IEEE 20th International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS). IEEE conference proceedings. ISSN 978-1-6654-2218-5. doi: 10.1109/PowerMEMS54003.2021.9658410.
• Aunet, Snorre (2021). Ultra Low Voltage Sub-100 mV Vdd CMOS. In Gauberts, Jean & Barragan, Manuel (Ed.), Proceedings, 19th IEEE Northeast Workshop on Circuits and Systems (NEWCAS), 2021. IEEE conference proceedings. ISSN 978-1-6654-2429-5. doi: 10.1109/NEWCAS50681.2021.9462735.
• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2021). Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider Applications. In Nurmi, Jari; Wisland, Dag Trygve Eckhoff; Aunet, Snorre & Kjelgård, Kristian Gjertsen (Ed.), Proceedings, 2021 IEEE Nordic Circuits and Systems Conference (NORCAS). IEEE. ISSN 978-1-6654-0712-0. doi: 10.1109/NorCAS53631.2021.9599871.
• Yassin, Yahya Hussain; Jahre, Magnus; Kjeldsberg, Per Gunnar; Aunet, Snorre & Catthoor, Francky (2021). Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode. Journal of Signal Processing Systems. ISSN 1939-8018. 93(1), p. 33–48. doi: 10.1007/s11265-020-01544-z. Full text in Research Archive Show summary

  Stringent power budgets in battery powered platforms have led to the development of energy saving techniques such as Dynamic Voltage and Frequency scaling (DVFS). For embedded system designers to be able to ripe the benefits of these techniques, support for efficient design space exploration must be available in system level simulators. The advent of the edge computing paradigm, with power constraints in the mW domain, has rendered this even more essential. Without a fast and accurate methodology for architecture simulation and energy estimation, the benefit of new ideas and solutions cannot be evaluated. In this paper, we propose a non-intrusive application controlled DVFS management implementation in the GEM5 simulator, used with GEM5’s system call emulation mode. We also propose a novel architecture independent energy model based on categorization of different measurable workload classes. Our energy model is parametrized and calibrated with power measurements on a SAM4L microcontroller board, containing an ARM Cortex M4 processor. Together with the GEM5 output statistics, the model accurately estimates the total energy consumption of our simulated system. The results from our modified GEM5 simulator are validated with representative signal processing applications. After correction of systematic offset errors, our results deviate with less than 4% compared to measurements from the SAM4L microcontroller. Our contributions in this paper can easily be tailored to other processor models in GEM5 and to future versions of GEM5. It will therefore enable system architects to explore new techniques and compare the improvements relative to existing architectures.

• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2020). An ultra low voltage subthreshold standard cell based memories for IoT applications. In Seyedarabi, Hadi (Eds.), Proceedings, 28th Iranian Conference on Electrical Engineering. IEEE conference proceedings. ISSN 978-1-7281-7296-5. doi: 10.1109/ICEE50131.2020.9260950.
• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2020). Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology. In IEEE, . (Eds.), 2020 IEEE Nordic Circuits and Systems Conference (NorCAS) . IEEE. ISSN 978-1-7281-9226-0. doi: 10.1109/NorCAS51424.2020.9265001.
• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2020). Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders. In IEEE, . (Eds.), 2020 IEEE Nordic Circuits and Systems Conference (NorCAS) . IEEE. ISSN 978-1-7281-9226-0. doi: 10.1109/NorCAS51424.2020.9265131.
• Låte, Even; Ytterdal, Trond & Aunet, Snorre (2020). Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping. IEEE Transactions on Very Large Scale Integration (vlsi) Systems. ISSN 1063-8210. 28(10), p. 2223–2227. doi: 10.1109/TVLSI.2020.3013139. Show summary

  This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally flipped during write operations to reach the more beneficial state for storage. A 1-kb SRAM block of low-voltage memory cells was implemented and manufactured in a 130-nm CMOS. The memory cells were made writable and read-stable at low supply voltages with a single-ended write and single-ended read structure using six multithreshold transistors that give rise to an asymmetric retention power. At a supply voltage of 350 mV, the content-dependent leakage power in the asymmetric memory cell is 23 times smaller when storing logic “1”s compared with logic “0”s. A derived statistical model suggests that the mean, wordwise, static power savings of the word-flipping scheme become 15.70% for 8-bit words of uniform bit probability. For the implemented SRAM macro, the mean improvement for the retention power is, including flip logic and decoder and driver overheads, found to be 14.69%. In boundary tests, by writing all words full of undesired values, the power saving becomes 80.37%, while writing all words full of desired values causes a power penalty of 6.14%. Measurement results confirm the improvement in retention power with a ten-chip mean improvement of 11.93% for the same data set.

• Låte, Even; Ytterdal, Trond & Aunet, Snorre (2020). An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V. IEEE Transactions on Circuits and Systems - II - Express Briefs. ISSN 1549-7747. 67(11). doi: 10.1109/TCSII.2020.2966654. Show summary

  We propose architectural advances in low voltage, energy efficient, level shifters. A write assist circuit is introduced,to support up-conversion of deep subthreshold inputs. We also present an approach to reduce the leakage current in split signal output stages. A prototype was created in a 130 nm bulk CMOS process, and some samples were successfully tested for input voltages as low as 5 mV. For 10 measured samples, the mean functional, minimum, input voltage was 31.1 mV. By applying body bias to selected NMOS transistors to compensate for process and mismatch variation, the measured mean minimum input voltage was lowered to 14.3 mV. The leakage reduction in the split control output driver reduces the driver leakage by a factor of 8. The designed level shifter was found to be energy efficient compared to published structures, it consumed an average of 25.9 fJ per conversion in post-layout simulations and the delay was measured to 21.08 ns at 300 mV input signals.

• Christensen, Steinar Thune; Aunet, Snorre & Qadir, Omer (2019). A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural Networks. In Nurmi, Jari; Ellervee, Peeter; Halonen, Kari & Røning, Juha (Ed.), 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE. ISSN 9781728127699. doi: 10.1109/NORCHIP.2019.8906950.
• Seyedi, Azam; Aunet, Snorre & Kjeldsberg, Per Gunnar (2019). Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications. In Nurmi, Jari; Ellervee, Peeter; Halonen, Kari & Røning, Juha (Ed.), 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE. ISSN 9781728127699. doi: 10.1109/NORCHIP.2019.8906911. Full text in Research Archive
• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2019). Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology. In Nurmi, Jari; Ellervee, Peeter; Halonen, Kari & Røning, Juha (Ed.), 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE. ISSN 9781728127699. doi: 10.1109/NORCHIP.2019.8906939.
• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2019). Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder. In Nurmi, Jari; Ellervee, Peeter; Halonen, Kari & Røning, Juha (Ed.), 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE. ISSN 9781728127699. doi: 10.1109/NORCHIP.2019.8906917.
• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2018). Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology. In Mihhailov, Juri & Jenihhin, Maksim (Ed.), Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE. ISSN 978-1-5386-7656-1. doi: 10.1109/NORCHIP.2018.8573516. Full text in Research Archive
• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2018). An Ultra-Low Voltage and Low-Energy Level Shifter in 28 nm UTBB-FDSOI. IEEE Transactions on Circuits and Systems - II - Express Briefs. ISSN 1549-7747. 66(6), p. 899–903. doi: 10.1109/TCSII.2018.2871637. Full text in Research Archive Show summary

  Abstract—A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used along with poly and back-gate biasing techniques to achieve an adequate balance between the drive strength of the pull-up and the pull-down networks. Measurements showed that the lowest input voltage levels, which could be upconverted by the 10 chip samples, varied from 39 mV to 52 mV. Half of the samples could upconvert from 39 mV to 1 V. The simulated energy consumption of the level shifter was 5.2 fJ for an up-conversion from 0.2 V to 1 V and 1 MHz operating frequency.

• Låte, Even; Ytterdal, Trond & Aunet, Snorre (2018). A loadless 6T SRAM cell for sub- & near- threshold operation implementedin 28 nm FD-SOI CMOS technology. Integration. ISSN 0167-9260. 63, p. 56–63. doi: 10.1016/j.vlsi.2018.05.006. Full text in Research Archive Show summary

  Most ultra low power SRAM cells operating in the sub and near threshold region deploy 8 or more transistors per storage cell to ensure stability. In this paper we propose and design a low voltage, differential write, single ended read memory cell that consists of a total of 6 transistors. The innovative idea is to bring the loadless 4-transistor latch into the realm of low voltage memory cells by exploiting features of the 28 nm FDSOI Process and by adding a 2-transistor readbuffer with a footer line. Stand-alone and on a system level, the cell is stable during read, write and hold operations and it has great write-ability due to its differential write and loadless nature. The single NWELL option in 28 nm FD-SOI allows the loadless core to have minimal device widths while greatly improving the time it takes to evaluate the read bit-line. The cell has, in this paper, been used in a 128 kb (2 17 ) SRAM in a 16 block configuration exploring 3 different types of logic libraries for the peripheral logic of the system. Depending on the application, the IO-peripheral logic may be implemented using either high threshold voltage transistors or low threshold voltage transistors in where the power consumption of the 128 kb system was found to range from 1.31 µW to 71.09 µW, the maximum operational frequency lies within 1.87 MHz and 14.97 MHz while the read energy varies from 13.08 to 75.21 fJ/operation/bit for a supply voltage of 350 mV. The minimum retention voltage of the loadless SRAM cell is found to be 230 mV covering 5σof variation with Monte Carlo simulations.

• Vatanjou, Ali Asghar; Låte, Even; Ytterdal, Trond & Aunet, Snorre (2017). Ultra-Low Voltage and Energy Efficient Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing. Microprocessors and microsystems. ISSN 0141-9331. 56, p. 92–100. doi: 10.1016/j.micpro.2017.11.002. Show summary

  Balancing the PMOS/NMOS strength ratio is a key issue to maximize the noise margin, and hence, the functional yield of CMOS logic gates and minimize the leakage energy per cycle in the subthreshold region. In this work, the PMOS/NMOS strength ratio was balanced using a poly-biasing technique in conjunction with back-gate biasing provided in a 28 nm fully depleted silicon on insulator (FDSOI) CMOS technology. A 32-bit adder based on minority-3 (min-3) gates and a 16-bit adder based on Boolean gates have been implemented. Chip measurement results of nine samples show highly energy efficient adders. The 32-bit and 16-bit adders achieved mean minimum energy points (MEP) of 20.8 fJ at 300 mV and 12.34 fJ at 250 mV, respectively. In comparison to adders reported in other works in the same technology, the energy per 1-bit addition of the 32-bit adder is improved by 37% . This improvement in energy consumption is 25% for the 16-bit adder. According to the measurement results of ten chips, the designed adders exhibited functionality down to supply voltages of 110 mV-125 mV, without body biasing. Additionally, the minimum Vdd of all the 32-bit adders based on minority-3 gates decreased to 80 mV by applying a reverse back bias voltage to the PMOS devices. One sample was functional at 79 mV with a 430 mV reverse back bias voltage applied to its PMOS devices.

• Låte, Even; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2017). Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI. Microprocessors and microsystems. ISSN 0141-9331. 48, p. 11–20. doi: 10.1016/j.micpro.2016.07.016. Show summary

  Nine D-type Flip-Flop (DFF) architectures were implemented in 28 nm FDSOI at a target, subthreshold, supply voltage of 200 mV. The goal was to identify promising DFFs for ultra low power applications. The single-transistor pass gate DFF, the PowerPC 603 DFF and the C2MOS DFF are considered to be the overall best candidates of the nine. The pass gate DFF had the lowest energy consumption per cycle for frequencies lower than 500 kHz and for supply voltages below 400 mV. It was implemented with the smallest physical footprint and it proved to be functional down to the lowest operating voltage of 65 mV in the typical process corner. During Monte Carlo (MC) process and mismatch simulations it was also found that the pass gate DFF is least prone to variations in both minimal setup- and minimal hold-time. Race conditions, during mismatch variations, occurred for the flip-flop that is constructed from NAND and inverter based multiplexers. The pass gate DFF is outperformed slightly when it comes to D-Q-based power-delay product and more significantly when it comes to the maximum clock frequency. The flip-flops having the shortest D-Q delays were the PowerPC 603 and the transmission gate D flip-flop, these also had the lowest D-Q-based power-delay of 26% and 30% respectively of that of the worst-case S2CFF power-delay product.

• Vatanjou, Ali Asghar; Låte, Even; Ytterdal, Trond & Aunet, Snorre (2016). Ultra-Low Voltage Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing. In Jørgensen, Ivan & Sparsøe, Jens (Ed.), Proceedings of the 2nd IEEE Nordic Circuits and Systems Conference (NORCaS), 2016. IEEE conference proceedings. ISSN 978-1-5090-1095-0. doi: 10.1109/NORCHIP.2016.7792895.
• Hasanbegovic, Amir & Aunet, Snorre (2016). Heavy Ion Characterization of Temporal-, Dual- and Triple Redundant Flip-Flops Across a Wide Supply Voltage Range in a 65 nm Bulk CMOS Process. IEEE Transactions on Nuclear Science. ISSN 0018-9499. 63(6), p. 2962–2970. doi: 10.1109/TNS.2016.2614781. Show summary

  In this paper, we investigate the single event upset (SEU) response of five D flip-flops (DFFs) employing temporal redundancy, dual redundancy, and triple modular redundancy (TMR), across a wide supply voltage range. The DFFs were designed and fabricated in a low-power commercial 65 nm bulk CMOS process and were tested using heavy ions with linear energy transfer (LET) between 5:1 MeV-cm2=mg and 99:1 MeV-cm2=mg. Results show an increasing SEU vulnerability with decreasing supply voltage, for most of the DFFs. Nevertheless, radiation tolerant topologies exhibit 14x to 1328x better SEU tolerance than a standard non-radiation tolerant DFF, depending on supply voltage and LET. The general observation is that at normal incidence, while taking the entire LET spectrum into account, the dual interlocked storage cell (DICE) DFF has the best SEU tolerance at supply voltages of 1 V and 0.5 V. At a supply voltage of 0.25 V, a temporal redundant DFF shows the best SEU tolerance, while the TMR DFF shows the best SEU tolerance at a supply voltage of 0.18 V. At supply voltages of 0.5 V and below, increasing the angle of incidence to 45 degrees can increase the SEU rate of the implemented DICE DFF by up to a factor of 22x, making it one of the most SEU sensitive DFFs. Furthermore, utilizing high drive strength components in temporally redundant DFFs can reduce the SEU sensitivity by a factor of 3x to 112x, compared to when standard drive strength components are used.

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2016). 28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block. In Napieralski, Andrzej (Eds.), Proceedings of the 23rd International Conference - "Mixed Design of Integrated Circuits and Systems" (MIXDES), Lodz, Poland. IEEE conference proceedings. ISSN 9788363578084. p. 105–110. doi: 10.1109/MIXDES.2016.7529711.
• Låte, Even; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28nm FDSOI. In Tørresen, Jim; Aunet, Snorre; Lande, Tor Sverre; Grutle, Øyvind Kallevik & Nielsen, Ivan R. (Ed.), Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015. IEEE conference proceedings. ISSN 978-1-4673-6576-5. doi: 10.1109/NORCHIP.2015.7364372.
• Atarzadeh, Hourieh; Aunet, Snorre & Ytterdal, Trond (2015). An Ultra-Low-Power/High-Speed 9-bit Adder Design: Analysis and Comparison Vs. Technology from 130nm-LP to UTBBFD-SOI-28nm. In Tørresen, Jim; Aunet, Snorre; Lande, Tor Sverre; Grutle, Øyvind Kallevik & Nielsen, Ivan R. (Ed.), Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015. IEEE conference proceedings. ISSN 978-1-4673-6576-5. doi: 10.1109/NORCHIP.2015.7364365.
• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). 4 Sub-/Near-Threshold Flip-Flops with Application to Frequency Dividers. In Larsen, Bjørn B. & Fey, Görschwin (Ed.), Proceedings, 2015 European Conference on Circuit Theory and Design. IEEE conference proceedings. ISSN 978-1-4799-9877-7. doi: 10.1109/ECCTD.2015.7300058.
• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Exploiting Short Channel Effects and Multi-Vt Technology for Increased Robustness and Reduced Energy Consumption, with Application to a 16-bit Subthreshold Adder Implemented in 65 nm CMOS. In Larsen, Bjørn B. & Fey, Görschwin (Ed.), Proceedings, 2015 European Conference on Circuit Theory and Design. IEEE conference proceedings. ISSN 978-1-4799-9877-7. doi: 10.1109/ECCTD.2015.7300053.
• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS. In Hamid, Inon Abdul; Chen, Yiren; Cher, Chen-Yong & Iranmanesh, Ali A. (Ed.), Proceedings of the 6th Asia Symposium on Quality Electronic Design. IEEE conference proceedings. ISSN 978-1-4673-7495-8. p. 7–12. doi: 10.1109/ACQED.2015.7273999.
• Hasanbegovic, Amir & Aunet, Snorre (2015). Supply Voltage Dependency on the Single Event Upset Susceptibility of Temporal Dual-Feedback Flip-Flops in a 90 nm Bulk CMOS Process. IEEE Transactions on Nuclear Science. ISSN 0018-9499. 62(4), p. 1888–1897. doi: 10.1109/TNS.2015.2454479. Show summary

  In this paper we investigate the efficiency of using temporal and spatial hardening techniques in flip-flop design for single event upset (SEU) mitigation at different supply voltages. We present three novel SEU tolerant flip-flop topologies intended for low supply voltage operation. The most SEU tolerant flip-flop among the proposed flip-flop topologies shows ability of achieving maximum SEU cross-section below 1.9 ·10-10 cm2 /bit (no SEUs detected) at 500 mV supply voltage, 4 ·10-10 cm2 /bit at 250 mV supply voltage, and 2 ·10- 9 cm2 /bit at 180 mV supply voltage. When scaling the supply voltage from 1 V down to 500 mV, 250 mV and 180 mV, the proposed flip-flops achieve at least - 72%, - 92.5% and - 95% (respectively) reduction in energy per transition compared to a Dual Interlocked Storage Cell based flip-flop when operated at a supply voltage of 1 V. The flip-flops have been designed and fabricated in a low-power commercial 90-nm bulk CMOS process and were tested using heavy ions with LET between 8.6 MeV-cm2 /mg and 53.7 MeV-cm2 /mg.

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• Nurmi, Jari; Wisland, Dag Trygve Eckhoff; Aunet, Snorre & Kjelgård, Kristian Gjertsen (2021). Proceedings, 2021 IEEE Nordic Circuits and Systems Conference (NORCAS). IEEE. ISBN 978-1-6654-0712-0. 220 p.
• Nurmi, Jari; Wisland, Dag T; Aunet, Snorre & Kjelgård, Kristian Gjertsen (2020). Proceedings, Sixth IEEE Nordic Circuits and Systems Conference (NorCAS 2020). . IEEE conference proceedings. ISBN 978-1-7281-9226-0. 205 p. Show summary

  On behalf of the Organizing Committee, we would like to welcome all of you to the Sixth IEEE Nordic Circuits and Systems Conference (NorCAS 2020). The conference is a merge of the well-established conferences NORCHIP and the International Symposium on System-on-Chip (SoC). We have a high-quality program with keynotes and papers to be presented. Research covering a wide range of topics within circuits and systems in the digital, analog and mixed domains will be presented. From in total 58 papers submitted, 29 papers were selected for oral presentation in the virtual conference, yielding exactly 50% acceptance rate. There will be four invited speakers who will share their view on emerging key technologies in the circuits and systems field. In the opening session Prof. An-Yeu (Andy) Wu from National Taiwan University will discuss compressive sensing and compressive analytics. Later in the afternoon Prof. Alberto Bosio from ICL, France, will give insights to approximate computing and, in particular, testing of it. In the second morning, Prof. Tim Constandinou from University College London, UK, will present his talk on “Future Human: Merging Minds and Machines.“ The final talk is given by Prof. Alexander Wyglinsky from Worchester Polytechnic Institute, USA, introducing an educational view to Software-Defined Radio. We would like to forward great thanks to IEEE Circuits and Systems Society (CAS) for financial co-sponsoring of the conference. Thanks also to Tampere University and University of Oslo for the efforts on the congress office and virtual platform. We are also thankful to all the Program Committee members and reviewers who have put time and effort into reviewing the submitted papers. Moreover, we are grateful to the NorCAS steering committee for helpful advice and their contribution in the paper selection process. We hope that you will enjoy your time in the virtual conference. We wish you an inspiring conference where your knowledge is increased and friendships are both established and strengthened.

• Tørresen, Jim; Aunet, Snorre; Lande, Tor Sverre; Grutle, Øyvind Kallevik & Nielsen, Ivan R. (2015). Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015. IEEE conference proceedings. ISBN 978-1-4673-6576-5. 275 p.

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• Su, Shengkai; Truong, Binh Duc; Aunet, Snorre & Le, Phu Cuong (2021). A reliable and wide-range tuning technique for low-frequency MEMS energy harvesters.
• Aunet, Snorre & Aunet, Snorre (2021). Ultra Low Voltage Sub-100 mV Vdd CMOS.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2021). Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider Applications.
• Aunet, Snorre (2021). Ørsmå energihøstende IoT-noder.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). 0 Comparative Study of Single, Regular and Flip well Subthreshold SRAMs in 22 nm FDSOI Technology.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). 0 Multi-threshold voltage and dynamic body biasing techniques for energy efficient ultra low voltage subthreshold adders.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). An ultra low voltage subthreshold standard cell based memories for IoT applications.
• Seyedi, Azam; Aunet, Snorre & Kjeldsberg, Per Gunnar (2019). Towards Compact Radiation Hardened Memories for Space Applications.
• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2019). Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology.
• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2019). Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2019). Ultra low voltage subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2019). Low Energy CMOS building blocks for IoT.
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2019). Low Energy CMOS building blocks for IoT.
• Aunet, Snorre (2019). Asynchronous ultra low voltage / low power CMOS - what and why, but not much about how. . Show summary

  Reducing the supply voltage to the subthreshold region, where the supply voltage is below the absolute values of the inherent threshold voltages, has been regarded the most direct and dramatic means of reducing overall power consumption. Full Custom logic and memory building blocks are needed to take full advantage of subthreshold operation, that may reduce power consumption by orders of magnitude, and energy per operation by typically 10 times or more, compared to normal super-threshold circuits. The lower the supply voltage, the lower the power consumption. Examples of a 32-bit RISC processor operating at subthreshold voltages, as well as arithmetic building blocks operating at supply voltages below 100 mV are mentioned briefly. The strong relationships between supply voltage and power consumption, as well as energy per operation, are due to several exponential relationships between voltages across nodes of the transistor, temperature and threshold voltages, in subthreshold operation. Dealing with process-, voltage-, and temperature (“PVT”-) variations is the greatest challenge when exploiting subthreshold techniques for ultra low power / low energy circuits. Circuit delays can vary by up to orders of magnitude, due to PVT variations. When the traditional synchronous circuits design paradigm is used, combined with subthreshold operation, necessary worst-case timing considerations leads to slowing down circuitry by up to orders of magntitude, while at the same time increasing power- and energy consumption radically, compared to superthreshold / strong inversion circuits. To fully exploit the low power / low energy potential of subthreshold circuits, asynchronous solutions not taking worst case behavior into account in the normal fashion, may be a key concept.

• Aunet, Snorre (2018). Possibilities with ultra low power / low energy integrated circuits.
• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2017). Ultra-Low Voltage/Energy CMOS Building Blocks in 28 nm FDSOI Technology.
• Aunet, Snorre (2017). Ultra-low power electronic circuits for medical applications.
• Aunet, Snorre (2017). Introduction to ultra-low power electronic circuits design.
• Aunet, Snorre (2017). Introduction to ultra-low power electronic circuits design.
• Aunet, Snorre (2017). Introduction to ultra-low power electronic circuits design.
• Tørresen, Jim & Aunet, Snorre (2017). Special issue: Selected papers from the 1st NORCAS conference (2015 Nordic Circuits and Systems Conference (NORCAS): Norchip & International Symposium on System-on-Chip (SoC)). Microprocessors and microsystems. ISSN 0141-9331. 48, p. 1–2. doi: 10.1016/j.micpro.2016.11.008.
• Vatanjou, Ali Asghar; Låte, Even; Ytterdal, Trond & Aunet, Snorre (2016). Ultra-Low Voltage Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing.
• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2016). 28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block.
• Aunet, Snorre & Tørresen, Jim (2016). Special issue: selected papers from the 1st NORCAS conference (2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium on System-on-Chip (SoC)). Analog Integrated Circuits and Signal Processing. ISSN 0925-1030. 89(2), p. 271–272. doi: 10.1007/s10470-016-0847-5.
• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS. Show summary

  This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (”RCA”), demonstrating functionality for a supply voltage ("Vdd") down to 84 mV. The low Vdd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32- bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80 nm, respectively. The implementation having 80 nm gate lengths exploits secondary effects like the Reverse Short Channel Effect (”RSCE”) to provide lower energy per operation, compared to the 60 nm implementation, when operated down to subthreshold supply voltages. Dimensioning for symmetric noise margins, and using minority-3 circuits and inverters only, with regular layouts, contribute to the ultra low Vdd potential. According to simulations, the energy per operation could be down to about 1.5 fJ/bit for the implementation, based on L = 80 nm. For delays in the 20 ns to 110 ns range, the energy consumption for the RCA having L = 60 nm, was from 18.5 to 47 % higher than the RCA having L = 80 nm. The area was 9.7 % less for the L = 80 nm implementation, compared to the L = 60 nm RCA.

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Exploiting Short Channel Effects and Multi-Vt Technology for Increased Robustness and Reduced Energy Consumption, with application to a 16-bit Subthreshold Adder Implemented in 65 nm CMOS. Show summary

  When using standard multi-Vt CMOS processes when making logic gates, often for example Low-Vt (LVT), or Standard-Vt (SVT) or High-Vt (HVT) transistors are used within one and the same basic logic building block, like for example a NAND or NOR circuit. We show, to the contrary, how a combination of different types within a single logic circuit may be exploited to reduce energy consumption and increase robustness towards process variations. Additionaly, Reverse Short Channel Effects (RSCE) are exploited by using non-minimum gate lengths for increased robustness agains process variations. Also, a recently proposed technique using very regular layouts accompanying the above mentioned techniques in a 16-bit adder implemented in 65 nm CMOS. Chip measurements using Sub-/Nearthreshold supply voltages demonstrate the functionality of the adder for a voltage range of 119 mV to 350 mV. Simulations show that by increasing gate lengths to 200 nm instead of the minimum 60 nm, may increase the footprint area of logic gates by only 12%, while at the same time reducing probability of failure by up to several orders of magnitude. Simultaneously, energy per operation is reduced, when compared to conventional design methods using minimum, or relatively short, gate lengths

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). 4 Sub-/Near-Threshold Flip-Flops with Application to Frequency Dividers. Show summary

  Four different flip-flops dimensioned for subthreshold operation have been designed and implemented in layouts. The four full custom, race-free, D-flip-flops were implemented in a standard 65 nm CMOS process and verified by measurements, when used in 2 divide-by-3 circuits. The first frequency divider, using standard topologies, demonstrated functionality down to a supply voltage of 132 mV, while the second variant, based on a recently proposed ”‘slice-based”’ approach, was functional for a supply voltage down to 137 mV. The frequency divider using traditional 4-transistor NAND and NOR topologies had lower energy per operation than the alternative 8-transistor NAND and NOR implementation. At 0.1 MHz, the figures were about 2.1 fJ and 3.5 fJ, respectively. For supply voltages from 0.2 to 1.2 V, a static flip-flop using 8-transistor NOR- gates plus one inverter had the lowest static power consumption among the 4 flip-flops.

• Låte, Even; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28nm FDSOI. Show summary

  Nine D flip-flop architectures were implemented in 28nm FDSOI at a target, subthreshold, supply voltage of 200mV. The goal was to identify promising D flip-flops for ultra low power applications. The pass gate flip-flop was implemented using 49% of the S2CFF's area and was functional at the lowest operating voltage of 65mV in the typical process corner. At the targeted supply voltage of 200mV the racefree DFF gives the best functional yield of 99.8%. The flip-flops having the shortest D-Q delays were the PowerPC 603 and the transmission gate D flip-flop. These also had the lowest power delay products of 52.08aJ and 61.09aJ respectively.

• Atarzadeh, Hourieh; Aunet, Snorre & Ytterdal, Trond (2015). An Ultra-Low-Power/High-Speed 9-bit Adder Design: Analysis and Comparison Vs. Technology from 130nm-LP to UTBBFD-SOI-28nm.
• Aunet, Snorre (2015). Ultra Low Power / Low Energy Integrated Circuits.
• Aunet, Snorre (2015). Ultra Low-Voltage / Low energy circuits.
• Værnes, Magne; Ytterdal, Trond & Aunet, Snorre (2014). Performance comparison of 5 Subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout.
• Bjerkedok, Jonathan Edvard; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2014). Modular Layout-friendly Cell Library Design Applied for Subthreshold CMOS.
• Hossein Zadeh, Somayeh; Ytterdal, Trond & Aunet, Snorre (2022). Energy Efficient Subthreshold Digital Building Blocks . NTNU. ISSN 1503-8181. Show summary

  Many IoT applications such as implantable biomedical devices, sensor nodes in the internet of things operate in the kHz range, and power consumption is the primary concern in such applications. However, the required voltage of the most implantable electronic devices is 2-3 V [47]. The output properties of the most recent in vivo energy harvesters (IVEHs) is 150 mV and below [47, 61] which could suit the low voltages for the subthreshold circuits, while saving energy by not having to use as energy costly DC-DC conversion as one would for higher supply voltages. Therefore, subthreshold circuits operating at the supply voltages lower than the absolute value of the threshold voltage of the transistors might be the best option for such applications. The power consumption is reduced as the circuit supply voltage is lowered down towards and below the threshold voltage of the transistors, but it will increase the propagation delays. It may not be a concern for low to medium performance. Voltage scaling in integrated circuits brings challenges for a designer that has to be considered during the design phase. The impact of the process, voltage, and temperature variations increases by voltage scaling and affects the functionality of the circuits. This thesis focuses on designing and exploring energy efficient computing and memory circuits at ultra low voltage subthreshold regime at the different abstraction levels. Techniques such as body biasing (reverse body bias), transistor stacking, device sizing, multi-threshold voltage devices at the gate level have been explored to reduce the power consumption especially static power, taking into account the reliability issue and process, voltage and temperate variations. At the circuit level, different topologies of the full adders based on the standard CMOS designed for subthreshold supply voltages have been compared considering the functionality and reliability issues. In addition, an optimal back gate bias has been proposed in a commercially available 22 nm FDSOI (Fully Depleted Silicon On Insulator) technology that minimizes the energy per operation consumption of subthreshold digital CMOS circuits and improves the reliability. The adder as a case study under optimal body bias consumes 4.67 percent less energy than zero body bias at Vdd=150 mV and a frequency of 1 kHz. At the architectural level, two different types of adders including Kogge iii Abstract Stone adder (KSA), the fastest adder, and the Ripple Carry adder (RCA), the simplest adder have been designed and fabricated for supply voltages as low as Vdd = 140 mV. The adders have been synthesized at the gate level using full custom standard cell library designed for ultra low voltage subthreshold regime. The gap between simulation and measurement results is filled with successful implementation and comparison of the ultra low subthreshold adders at such a low voltage 140 mV. To the best of the authors knowledge this is the first measurement comparison between two different adder architectures for ultra low supply voltages as low as 140 mV. Simulated results in [7] indicated that the RCA is 1.36X energy efficient compared to the KSA at the same speed. Measured results presented here, show that the RCA is 4.15X to 1.92X energy efficient compared to the KSA at supply voltages between 250 to 500 mV. In addition, the RCA designed in this study outperforms the reported works in terms of a defined FoM which is (T ech)/(Vmin.Energymin). Digital circuits designed for applications like sensor networks, implantable biomedical devices and environmental monitoring need to work at different conditions. For example, the temperature range that circuit should work. In this thesis, we have studied the performance of the circuits at different temperatures, supply voltage and in the presence of mismatch and process variations. <further contents not included due to space limitations>

• Steinsland, Christian Rosioara; Aunet, Snorre & Ytterdal, Trond (2021). Design and Implementation of a Digital Standard Cell Library for 28 nm Technology. NTNU. Show summary

  A digital standard cell library has been designed and implemented for a 28 nm technology. The library has been designed and optimized for a supply voltage of 300 mV, to be compatible with a standard design flow. Each cell has been characterized with extracted parasitic components. Combinatorial logic gates, including compound logic gates, and sequential cells were implemented with SLVT (Super Low VT) transistors. The library has been used to synthesize a functional RISC-V architecture (PicoRV32). The motivation was to verify the functionality of the standard cell library and obtain quantitative results of the performance of the library. The minimum energy point (at room temperature in the TT-corner) for the CPU was found to be with a supply voltage of 500 mV and a frequency of 20 MHz. By increasing the supply voltage to 600 mV, the CPU supports a 50 MHz clock. The highest simulated frequency was 250 MHz at 1 V

• Rud, Markus; Moldsvor, Øystein & Aunet, Snorre (2021). Power and energy consumption in hardware implemented SPI master devices. NTNU. Show summary

  This thesis presents an analysis of two different VHDL designs of the SPI master device implemented onto a model of a FPGA. The analysis is focused at power and energy consumption in the devices compared with provided functionality. The two devices differ in their design strategy where one is created as a simple design where only the required logic to conduct a SPI transmission are implemented. The second one is a more complex design where it is possible to adjust transmission parameters such as setup and hold time after implementation and a more complex interface to the controlling logic which controls the SPI masters. The complex implementation also implement two FIFO registers to store multiple messages during transmission and reception. The conducted analysis is based upon different tests in order to give an understanding of which elements of a SPI master who impact the energy consumption in the device. These tests look into the impact of operating frequency, communication frequency, operation mode and alternation to the utilized logic. The designs are implemented onto a model of a FPGA using the development tool Vivado. The two designs are also power optimized using the build in power optimizer in Vivado. The results from the analysis show that when implementing a SPI master, it is necessary with a trade of between functionality and energy consumption. The different implementations are analysed over a frequency span of 1 MHz to 15 MHz where it is seen that the complex master requires 27.2% more energy than the simple master on average. It is therefore seen that a higher complexity in the design requires more energy. The complex master utilize more than twice as much logic, but not twice as much energy, so the energy cost of added functionality is therefore heavily dependent on the switching activity in the added logic. The results also show that it is preferable to operate the tested SPI masters at the highest frequency possible within the tested frequencies since this gives the lowest energy consumption. This result is to some extend limited by the implementation method as the implementation of the SPI master onto a FPGA removes some potential benefits of operating the design at a low frequency such as smaller transistor sizes and lower operating voltage. It is also seen that the two SPI designs react relatively similar to adjustments to transmission parameters such as communication frequency and operating mode since their percentage energy difference with adjustments are approximately similar for both designs. The analysis consist of some limitations. The SPI masters are analysed as standalone devices not connected to any controlling device which limits the energy analysis due to missing timing delays. The SPI masters are also relatively small designs so when implemented on a large FPGA compared to the designs, a large static power overhead is added which can hide the actual static power consumption for the designs themselves.

• Nielsen, Auseth, Øivind; Aunet, Snorre & Ness, Torbjørn Viem (2021). Modelling of Cache/Interconnect Performance in an Embedded System. NTNU. Show summary

  The cache and bus topology in an embedded system has a big influence on the system performance and energy efficiency. Producing a new silicon chip for testing is expensive, and this has made simulating architectural changes a common practice in the industry. Modern RTL simulations are able to provide highly accurate estimates of integrated circuit performance. However, modelling an architecture for such a simulation is a long and laborious process, and making modifications to the model is often time consuming. There is a need for a quick and easy way of experimenting with different bus topologies, which is still able to provide a good estimate of how various changes will affect performance. This thesis presents an easy to use model, which allows for completely changing an architecture just by modifying a few values in a text file. The model uses a node tree representation of the bus hierarchy, abstracting away hard to model architecture features, such as timing jitter when crossing between clock domains, and bus contention. Each node represent a component in the interconnect topology and explicitly states the latency it contributes to a memory access. This allows a highly simplified architecture description to be written, only focusing on the aspects of the bus topology which significantly contribute to memory access performance. The bus topology simulated for testing purposes in this thesis is the main Cortex-M33 processor on Nordic Semiconductor's nRF5340 SoC. The simulation results were compared to tests running on a nRF5340 development kit. When simulating Coremark with cache enabled, the model reported a 18.70\% longer run time than hardware. When simulating Coremark with cache disabled, the model reported a 4.36\% longer run time than hardware. When simulating sequential accesses to matrices, the model reported 68\% more instruction cache hits and 18\% fewer latency cycles than hardware for the smallest matrices, and 50\% more instruction cache hits and 5\% fewer latency cycles than hardware for the largest matrices. The model displayed high fidelity, but the simulated results were offset from the hardware results. It is useful for predicting whether a change would lead to an increase or decrease in instruction cache performance and total latency cycles. There were issues outside the scope of this thesis which were significant error sources in the results. In preliminary testing of how the model would perform if these issues were resolved, it reported cache hit and cache miss results which were within 0.2\% of the results seen on hardware, and cache latency results which were 7.3\% higher than the results seen on hardware. This shows that the model has the potential to achieve very accurate results, and be a useful tool for initial exploration of the performance impact of modifications to cache and bus topology.

• Skavnes, Solveig; Moldsvor, Øystein; Hagen, Anders Ivar & Aunet, Snorre (2021). Design and Implementation of a Magnetic Energy Harvesting System for Low Primary Current Applications. NTNU. Show summary

  Energy harvesting is the act of exploiting small amounts of ambient energy to power a low power system, like a sensor node. This can be done from the magnetic fields originating from an AC current, Ip, flowing through a power cable. The aim of this thesis is a system that is able to deliver 3.3 V to charge a battery, while Ip is under 1 A. The system should work for Ips under 1 A, since this will allow it to charge a battery a lot of the time even if the cable it is connected to is not carrying high AC currents. A magnetic energy harvesting system can consist of a current transformer (CT), a rectifier and a DC/DC converter. Such a system is designed, simulated using SPICE and implemented using components on a breadboard. The different sub-systems are tested individually and together. Five different commercial CTs are tested. Three different rectifiers are designed and tested, and two DC/DC converters are tested. This makes a total of 30 sub-system configurations, of which three fulfil the requirement of working at Ip < 1 A. The combination of sub-systems that manages to deliver 3.3 V to a battery on the lowest Ip is the combination of a CT with a 1:2000 turn ratio, a schottky diode rectifier and a high input resistance DC/DC converter. This system delivers 3.3 V to an attached battery at Ip = 0.5 A. It is tested and verified that the three sub-system configurations that work at Ip < 1 A continue to work up to Ip = 16 A. A commercial energy harvesting system with a combined rectifier and DC/DC is tested with the five CTs under the same conditions as a comparison. This is the LTC3331, and together with the best performing CT, it requires Ip = 5 A to deliver 3.3 V to a battery, making the commercial solution significantly worse than the system designed in this thesis.

• Rotevatn, Synnøve Andersen; Barzic, Ronan & Aunet, Snorre (2021). Automated Desynchronization Using Pyverilog. NTNU. Show summary

  Asynchronous circuits are inherently more robust to delay variability than the more common synchronous circuits. Automated desynchronization allows for making asynchronous circuits by removing the global clock and replacing it with handshake circuitry, without changing the design flow. The changes in the Verilog code needed to desynchronize a synchronous circuit into a simple Muller pipeline are presented. An implementation in Python using Pyverilog is made to automate that process. It is tested on two small designs. One is a linear pipeline consisting of just registers, and the other is a non-linear pipeline with a fork, a join and combinational logic. The implementation succeeds in transforming the designs into asynchronous circuits, and both pipelines pass tests that are comparable to the tests of the original circuits. However, the simplicity of the type of asynchronous circuit that is chosen means that the functionality is not equivalent to the original. Lastly, the implementation is tested on a RISC-V CPU core. All the same changes are made as with the smaller designs, but the solution is not advanced enough to handle such a complex circuit. A number of limitations to the current implementation are identified, which would need to be improved to have useful, automated desynchronization. The method is not optimal for all cases, but can be the most useful for someone who has full control of the coding style of the circuit they are desynchronizing.

• Aunet, Snorre; Ytterdal, Trond; Lande, Tor Sverre & Moulin, Kaspar Sigurd (2021). Low-Power Neuromorphic Sound Source Localization. NTNU. Show summary

  In this thesis, we present a neuromorphic approach to the sound source localization problem, based on the Jeffress model of sound source localization. The proposed system uses binary neural spike coding and asynchronous axonal delay lines to efficiently compute the cross-correlation in the time domain and determine the interaural time delay (ITD) between binaural input signals. While more research is needed, the proposed approach potentially offers significant improvements over current hardware implementations, with regards to power consumption and response time. In the test cases simulated, the system estimates the ITD to within 10us, with an average power consumption of 350nW. Simulations also showed a sub-millisecond reaction time to changes in the ITD. However, the proposed system is highly dependent on accurate component matching for proper functioning, and we find that additional compensation techniques would be required for a fabricated chip.

• Låte, Even; Ytterdal, Trond & Aunet, Snorre (2021). Low Voltage Logic and Memories on Silicon. NTNU. ISSN 978-82-326-6512-9. Show summary

  https://ntnuopen.ntnu.no/ntnu-xmlui/handle/11250/2740488

• Schoepe, Felix Allan; Gamst Reichelt, Pål Øyvind & Aunet, Snorre (2020). Ultra-low power accurate temperature sensor for IoT. NTNU. Show summary

  The analog front-end of a proposed BJT-based temperature sensor has been designed. The design has been analysed using Monte-Carlo simulations with mismatch over all process corners. The design was implemented in a 90nm generic process design kit. The analog front-end achieves ultra-low power consumption with a current consumption of 2.3 mA at a temperature of 27 °C and can operate over the military temperature range of -55 °C - 125 °C. It uses a voltage supply of 2 V. An adaptive self-biasing operational amplifier was implemented in the bandgap reference circuit to ensure sufficiently high DC loop-gain. It operates on an ultra-low current consumption of 631 nA. To reduce errors due to mismatch and process spread two correction techniques have been employed, that is chopping of the input signals of the operational amplifier and dynamic element matching of the current sources in the bipolar core. The residual temperature reading error at the output of the analog front-end is large and results in significant errors. This is because no compensation technique was implemented in the analog front-end to compensate for process spread of the BJTs and should be implemented digitally. The temperature reading errors due to offset and mismatch in the current sources have been reduced to around 0.03 °C at a temperature of 27 °C. The noise in the circuit was analysed without the dynamic effects of the DEM because of its simple implementation and results in an equivalent temperature error of around 0.12 °C, which indicates the resolution that is achievable. The settling time of the circuit is in the range of 110 ms.

• Bygland, Embla Trasti; Austbø, Knut & Aunet, Snorre (2020). Power Modeling of Complex Designs. NTNU. Show summary

  In this project, a tool for making power models of designs at the Register Transfer Level (RTL) is implemented. The generated power model is intended to be used with a power estimation tool, to give an early, fast and accurate power estimate. Nordic Semiconductor ASA issues this masters project with the motivation of making RTL simulations poweraware. Discovering power bugs early in the implementation of a design may save iterations in the Application Specific Integrated Circuit (ASIC) design flow, and thus reduce time to market for a product. The method for estimating power at the RTL called the top-down method was chosen for the implementation. Among other desired qualities, it does not require a gate-level representation of the design to produce a power estimate. This allows for power estimation to be done concurrently to simulations for functional verification of the RTL, before synthesis of the design. The power modeling problem is divided into three tasks: 1. Extracting structural information from an elaborated SystemVerilog representation of the design. 2. Extracting information about available cells and their power consumption characteristics from the cell library. 3. Combining the structural representation with the cell- and power information retrieved, in order to create a power model. In the implementation, the structure of the design is represented by a node tree, while a cell library object was created to represent available cells from the cell library and their power data. In order to produce a power model, the implementation takes sequences of generic cells from the structure tree and replace them with cells obtained from the cell library. The power model consists of several power-aware node trees. The power model representation is more similar to the gate-level netlist than the elaborated SystemVerilog representation. However, more work is needed to obtain a proper comparison between them. The implementation shows promise for accurate and fast power estimation. Several abiii stractions are done in the process so that fast estimations can be made, and their effect on the power consumption have been evaluated together with other alternatives. When creating the power-aware node tree, cells from the generic cell library are grouped to more complex cells from the cell library. This grouping ensures a reduction in the number of cells, which brings the model closer to the gate-level representation. Some work remains to complete the power model; the most complex generic cells from the elaborated SystemVerilog file need to be constructed from several cells from the cell library. Complex cells with no equivalent yet are those representing arithmetic operations, shifters and comparators. When these cells have a representation, switching activity can be propagated through the structure trees in order to get a power consumption estimate for each of them. The final job of the power estimation tool is to solely use the activity data from the RTL simulation, together with the power values from each structure tree to yield the power estimate.

• Dieset, Herman Kristian; Qadir, Omer & Aunet, Snorre (2020). Approximate Arithmetical Operators for Energy Efficient Inference in Deep Neural Networks. NTNU. Show summary

• Gausdal, Kaja; Gonsholt, Kyrre Erlend; Qadir, Omer & Aunet, Snorre (2020). Applying Asynchronous Completion Detection to the AVS Domain. NTNU. Show summary

  Power consumption has become one of the leading challenges designers face as technology continues to scale. Classical worst-case corner analysis is overly pessimistic, since increasing PVTA variations must be compensated for by excessive safety voltage margins. Certain AVS approaches minimize power consumption by monitoring the circuit's timing with error detectors and adapting the supply voltage to the chip's actual operating condition, consequently eliminating the need for excess voltage margins. Asynchronous completion detectors share many similarities with AVS error detectors. This thesis aims to evaluate the feasibility of applying a selection of bundled-data and dual-rail completion detectors to the AVS domain. Through a qualitative analysis, the asynchronous dual-rail scheme was deemed most suitable for adaptation due to its robustness towards PVTA variations. A novel dual-rail AVS approach was proposed, aiming to reduce unnecessary voltage margins by implementing a QDI dual-rail error detector. A dual-rail RTL library was constructed and used to map a single-rail MAC into a dual-rail function block. Sixteen function block variants were implemented and compared to a single-rail reference. The functionality of the error detector was verified through simulation, and results show the power, area, and timing overhead of the error detector to be either relatively constant or converging towards a lower bound for higher input size. The area and power overhead of the error detector are considered manageable and not a diminishing factor. Through tighter timing constraints, the timing overhead of the error detector critical path was minimized. A dual-rail technology library was proposed as a way to minimize area, power, and timing overhead. The synthesized error detector showed violations of QDI constraints, which compromise the robustness of the system. Actions were suggested to correct the violations, but due to the lack of appropriate tools, the overall robustness of the system was hard to quantify. The implemented dual-rail error detector was concluded to show promise as a proof of concept, and directions for future work were given.

• Fini, Simone; Ytterdal, Trond; Aunet, Snorre & Lavagno, Luciano (2019). Sub-Threshold Design of Arithmetic Circuits: when Serial might overcome Parallel Architectures. NTNU. Show summary

  Adder circuits are vital for microprocessors; indeed, apart from the addition itself, either subtraction, multiplication or division algorithms may require, at a certain point, the addition of two (partial or not) operands. For this reason, several architectures have been studied and improved over the last decades, in order to speed up the aforementioned operation. On the other hand, it is well known that having faster circuits means higher complexity, and, therefore, higher power consumption. In addition to this, the downscaling process of transistors has increased the leakage current of these devices, accounting for up to 33% of the total dissipation, and due to the little capabilities of batteries with respect to the achievable performance of circuits, the main challenge of engineers and designers is represented by exploiting low power techniques so as to decrease the power consumption of electronic devices as much as possible. This Master’s Thesis work wants to demonstrate that, when working in sub-threshold region, it might be possible to employ simple and repetitive circuits, like ripple carry adders, instead of complex ones, such as Kogge-Stone architectures, having the same propagation time but with a significantly lower energy consumption. In this way, it would be possible to have, at the same time, the performance given by a fast adder and the area and energy dissipation of the simpler and weaker "anchestor". As an anticipation, and as it will be seen in the final results, the technology employed and the choice of the best available architecture resulted in a great improvement with respect to the study previously conducted. First of all, with the development of a new full adder circuit (the so called "XMAJ3"), it is possible to reduce the energy consumption with respect to ripple carry adders based on both already existing architectures and on the full adder cell contained in the library. This even without the employment of customized gates, but only with standard logic blocks already contained in the library. Secondly, FDSOI technology makes possible to equalize performance of serial and parallel adders and, at the same time, saving energy, even in super-threshold region, allowing to avoid all the problems that subthreshold design brings. Particularly, for 32-bit based devices, the average energy saving with respect to the Kogge-Stone adder accounts for 41.48% (with a peak of 56.16%), while for 64-bit adders the mean saving is 50.02%, with a maximum of 56.83%.

• Boland, Connor; Aunet, Snorre & Moldsvor, Øystein (2019). Low Power Environmental Air Quality Monitoring. NTNU. Show summary

  Measuring personal environmental air quality is becoming increasingly relevant in today's society. Traditional monitoring requires oversized, expensive instruments, with slow and intensive sampling methodologies. Scalable, low-cost monitors are required to replace these outdated designs, to increase global access to air quality data. Disruptive Technologies provides long lifetime IoT solutions, specialising in smart wireless sensors. The aim of this project is therefore to develop a battery-operated environmental air quality monitor, with lifetime standards in line with those at Disruptive Technologies. The monitor must not only be able to measure a number of harmful air contaminants but also to measure the quality of the working environment. Specific emphasis on particulate matter sensing will provide a monitor with commercial viability. A number of particulate matter sensors were introduced. Initial current measurements on each were conducted to test their individual feasibility as part of a complete battery-powered monitor. Out of all of the tested sensors, only the Sharp GP2Y10AU0F compact optical dust sensor showed low current consumption for battery operation. A number of techniques to reduce this power consumption were introduced as part of a test design with the Sharp sensor and a microcontroller. Overall the calculated energy requirement for the sensor came to 1 638J for a two year lifetime. This was combined with two other sensors (one sensor measuring both volatile organic chemicals (VOC) and carbon dioxide (CO2), and the other sensor measuring both temperature and humidity) as a model of the complete energy requirements for the monitor. The total calculated energy consumption came to 125 968J, far exceeding a standard battery capacity of up to 39 960J. The unforeseen power limitation of this design was with the chosen VOC sensor, however, the project has still shown feasible opportunities for a battery powered environmental air quality monitor capable of measuring particulate matter.

• Christensen, Steinar Thune; Aunet, Snorre & Qadir, Omer (2019). En Konfigurerbar og Fleksibel Arkitektur for Laveffekt, Energieffektiv Maskinvareakselerasjon av Nevrale Nettverk basert på Foldning. NTNU. Show summary

  Convolutional neural networks (CNNs) have become paramount in today’s Artificial Intelligence (AI) and Machine Learning applications. This is true for image recognition in particular. This thesis presents a configurable, versatile and flexible architecture for hardware acceleration of CNNs that is based on storing and accumulating the entire feature maps in local memory inside the accelerator. This has been done while aiming to be able to process any type of CNN while consuming as low power as possible and achieving the highest possible energy efficiency, which refers to the number of operations per unit energy (measured in Multiply-Accumulate operations per unit energy, MACs/s/W or MACs/J). Several different versions of the architecture have been synthesized and tested using different configurations. It performs well when compared to the state-of-the-art, achieving an improved energy efficiency of over a factor 5 for select CNN layers. The most efficient configuration achieves 175 GMACs/s/W, while consuming 2.3 mW of power and occupying 585 KGEs (Kilo Gate Equivalents) of area at 1V supply voltage and a 100MHz clock. This is a significant improvement over Eyeriss [YuH17b] (a state-of-the-art accelerator) which has a maximal energy efficiency of 122.8 GMACs/s/W.

• Paintsil, Wesley Ryan; Aunet, Snorre & Moldsvor, Øystein (2019). A comparative study for commercial TVOC sensors. NTNU. Show summary

  Indoor air quality has become more important as human activity is increasingly spent inside. Internet of things has allowed for humans to better interact with the physical world by extracting information through sensor nodes. Indoor air quality sensors of different types have become increasingly popular, this thesis focuses on total volatile organic compound sensors. Three different sensors have been chosen and their operations evaluated by their power consumption. The Bosch BME680 proved to be the best sensor in terms of low-power, it had a lifetime of 4847 days as an alarm system and a lifetime of 2403 days if it acted as a monitoring system. The Integrated Devices Technologies ZMOD4410 only had a lifetime of 8 days. The AMS CCS811 had a lifetime of 871 days as an alarm system and 191 as a monitoring system. The BME680 had an integrated humidity and temperature sensor which provided an advantage by letting the host controller sleep longer. It should be possible to drive the BME680 and the CCS811 sensor with a 230mAh battery for more than 2 years.

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2019). Ultra Low-Power/Low-Energy CMOS Mixed-Signal Building Blocks. NTNU. ISSN 978-82-326-4322-6.
• Choe, Ju Song; Gheorghe, Codin & Aunet, Snorre (2018). Test system design for a Photomultiplier Readout Board. NTNU. Show summary

  The S-DAM front-end board (S-DAM-FEB) is a photomultiplier readout module for charged particles detection. This board has been designed for the readout of sensors in radiation monitors by the company, Integrated Detector Electronics AS (IDEAS). A large amount of S-DAM-FEB will be used in the neutron detector in the ESS (European Spallation Source) in Sweden for scientific research. Thus, hundreds of these modules are planned to be manufactured by third party of EMS (Electronic Manufacturing Service) and each board has to be validated after production. To be able to validate the DUTs efficiently, it has been decided to create a test system. In this thesis, the main focus was on the implementation of the test system to validate the functionality of the S-DAM-FEB. The project work included specifying the test requirements, conceptualization of the test system, schematic design and PCB design of needed hardware as well as implementing firmware and software for the test system. The needed Python scripts were created to run the test and log the test results into a test report. The mechanics of the test system was modelled by drawing a 3D-model, and the mechanical components were chosen according to the drawings. After implementing all the modules to be used for the test system, these modules were assembled together. The S-DAM-FEB was tested using the implemented test system. All functionality of the DUT was tested, including power consumption and temperature as well as gain, threshold and baseline for all channels. Minor fault in the DUT were found by the test, indicating that some failure has occurred during the production process. All the test results were logged into a test report for tracking the modules for future use and determine the condition of DUTs after production. The test system is in a working condition. Performing the validation test simple and easy. The runtime of the test is decreased, and most of the manual work is replaced by automatized process to get more reliable data and minimize possible human errors. The implementation of the test system was successful, and a large amount of S-DAM-FEB are ready to be validated.

• Østerhus, Stian; Ytterdal, Trond & Aunet, Snorre (2018). Subthreshold CMOS Cell Library by 22 nm FDSOI Technology. NTNU. Show summary

  Two different CMOS transistors with a low threshold voltage, given by a commercial available 22 nm FDSOI CMOS technology were investigated and assembled into several libraries of logic gates. The logic gates provided in the cell library should be sufficient to create most digital logic circuits, and are in addition designed to work in the subthreshold region with a supply voltage of 350 mV. Physical layout designs were made for the different digital ports, where parasitic capacitances were then extracted to provide more realistic simulations and performance results. Compared to schematic simulation, layout design and parasitic capacitances proved to reduce speed by a factor of 5 to 10, as well as increasing the transistors’ threshold voltage by 14.6 % for the NMOS, and 32.5 % for the PMOS. The increased threshold voltage thus led to a reduced static power consumption and increased switching energy. The transistor with the lowest threshold voltage showed especially good performance results with respect to low power consumption while still maintaining speed requirements. This transistor is throughout the report referred to as mosfet low. Two cell libraries were made for this transistor, where one applies a forward body-bias of ±2 V while the other have the bulk nodes connected to ground, which gives a 0 V body-bias. The libraries are supplied with schematics and layout designs, and are in addition mapped for performance data such as static power consumption, delay and switching energy consumption for every logic gate. A minimum speed of 40 MHz with a lowest possible power consumption for a 16by12-bit adder, was the aim of the project. Presented in this report is a 16by12-bit Adder built by Ripple-Carry Adders, which were simulated to reach a speed of 44.26 MHz at a supply voltage of VDD=350 mV with 0 V body-bias. Static power and switching energy consumption were simulated to 26.60 µW and 207.95 fJ, respectively.

• Stubsjøen, Sivert; Moldsvor, Øystein & Aunet, Snorre (2018). Force measurement using a capacitive sensor and a compressible material . NTNU. Show summary

  Disruptive Technologies are developing sensor solutions for the Internet of Things. Their current sensors can measure touch, temperature, and proximity. To expand the area of applications their current sensors cover, new sensor solutions are examined. The one studied in this thesis is a capacitive sensor measuring force. The idea is to place a compressible material on the front of Disruptive Technologies capacitive proximity sensor and use it to measure force. A compression of the material would lead to an increased capacitance measured. This thesis covers the work of finding suitable materials and the practical measurements done to characterize the capacitive sensor and the compressible material. Testing was done at two different materials that had properties useful for the intended application. These tests revealed that neither of the materials was optimal for a solution as described above. For different series of measurements, the values measured by the sensor variated for the same applied load. This made the work of creating a good fitting data model difficult. The proposed models could not predict with high probability the values measured by the sensor for the various applied loads. This lead to the conclusion that either the materials or the chosen sensor solution was not the optimal one for measuring force. As a result of this, two other force sensing methods using the same sensor is presented that can be further investigated in future work.

• Paldas, Auritro; Barzic, Ronan & Aunet, Snorre (2018). Towards Predictable Placement of Standard Cells for Regularly Structured Designs. NTNU. Show summary

  A lot of components in modern digital designs have very regular structures. Some examples are Programmable Ring Oscillators, Time to Digital Converters and CPU register files. The proper functioning of these components heavily depend on the way they are implemented in the design with respect to the placement of standard cells. This is due to the fact that many of these components are delay sensitive and the placement of cells in the layout affects the delay. Standard place and route tools, however, do not always ensure that the placement of standard cells is regularised, which can lead to sub-optimal results from these designs. The work on this thesis is aimed towards ensuring a regular placement of standard cells for such components, by developing a framework in a high-level language, from which the placement information needed by the place and route tools can be obtained. This information, when used by the tool, should result in a more predictable placement of standard cells, and should thus result in more optimal behaviour of such components.

• Rørstad Helle, Even; Moldsvor, Øystein; Hernes, Bjørnar & Aunet, Snorre (2018). Humidity Sensor. NTNU.
• Lesund, Martin; Tjora, Sigve & Aunet, Snorre (2017). Ultra-low power serial communication for Internet of Things. NTNU.
• Lid, Gunnar; Hagen, Anders; Blekken, Brage; Ytterdal, Trond & Aunet, Snorre (2017). Ultra-low power Design of DSRC modulator/demodulator in 28nm FD_SOI. NTNU.
• L'Orange, Simon; Hagen, Anders; Blekken, Brage; Ytterdal, Trond & Aunet, Snorre (2017). 4-7Ghz Tunable Programmable Pulse Generator in 65nm CMOS. NTNU.
• Hasanbegovic, Amir; Siem, Sunniva; Søråsen, Oddvar & Aunet, Snorre (2017). Exploring the SEU Dependence on Supply Voltage scaling in 90 nm and 65 nm CMOS Flip-flops. Universitetet i Oslo. Full text in Research Archive
• Liknes, Kai Robert; Hernes, Bjørnar & Aunet, Snorre (2016). Ultra Low Leakage Memory. NTNU. Show summary

  Three 64-byte memory systems were designed for a 0.18µm standard CMOS technology, one 6T-SRAM system and two D-Flip-Flop systems. The leakage current, read energy and write energy of these systems were determined by simulation. A set of extrapolation formulas for area, leakage current, read energy and write energy were designed to determine the characteristics of the systems as the size of the memory increases. The simulations showed that the 64-Byte 6T-SRAM system had a 39% lower area, an 83% lower leakage current, an 89% lower write energy and an 82% lower read energy than the reference D-Flip-Flop memory system. The extrapolation formulas predicted that as memory sizes increases, SRAM becomes more and more favorable in terms of area, leakage current, write energy and read energy.

• Barua, Anomadarshi; Edwin, David & Aunet, Snorre (2016). Voice over mesh network. NTNU.
• Kvam Oma, Åsmund; Låte, Even; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2016). Design of a near-threshold microcontroller. NTNU. Show summary

  There is a strong interest in ultra low voltage digital design as emerging applications like Internet of Things, wearable biomedical sensors, radio frequency identification, sensor networks and more are gaining traction. This thesis describes the implementation, synthesis and testing of a microcontroller using a near-threshold library. The system has been described in VHDL and synthesized for near-threshold operation on 28 nm FDSOI production technology from STmicroelectronics. The microcontroller implements a 32 bit RISC-V subset compatible pipelined processor and has SPI connectivity. Two single port 2kB SRAM modules are used as RAM. A power gating technique that reduces the static power in an ALU during runtime has been implemented and compared to a traditional ALU. Traditional coarse grain power gating of the processor has also been implemented. Using a supply voltage of 350 mV and a clock speed of 1 MHz the schematic SPICE simulation reported an average power consumption of 4.42 mW during program execution. In power gated mode the microcontroller consumed 2.98 mW. In a sensor logging program the average energy per executed instruction was 4.91 pJ. Runtime power gating reduced the average energy consumption of the ALU with 58 - 57% with a propagation delay penalty of 346 - 143% depending of the sizing of the power gating transistors.

• Zapatero, Miguel & Aunet, Snorre (2015). Synthesis of low-energy near-threshold SHMAC processor core. NTNU.
• Hals, Erik; Aunet, Snorre; Ramstad, Tor Audun; Hagen, Anders & Blekken, Brage (2015). Lav effekt sensornettverk, for registrering av kjøretøy. NTNU.
• Holen, Aslak Lykre; Ytterdal, Trond & Aunet, Snorre (2015). Implementation and Comparison of Digital Arithmetics for Low Voltage / Low Energy Operation. NTNU.
• Talstad, Joar Nikolai; Diaz, Isael; Øye, Jan Egil & Aunet, Snorre (2015). Channel Filter Cross-Layer Optimization. NTNU, Department of Electronics and Telecommunications.
• Pedersen, Arne Olav Gurvin; Gheorghe, Codin & Aunet, Snorre (2015). Design of an ASIC Evaluation Kit - Conceptualization, schematic design, PCB layout and preliminary testing of a mixed-signal board. NTNU, Department of Electronics and Telecommunications. Show summary

  The development of an upcoming ASIC by the company IDEAS calls for the design of an accompanying evaluation kit so that it may be accessible for testing in a laboratory setting. In addition to supporting the ASIC in question, the kit was decided to be made general purpose, leading to the support of various other ASICs from IDEAS, both future and existing ones. This thesis focuses on the creation of the primary board in the evaluation kit, named the Galao board. The project work included conceptualization, schematic design and PCB design of the Galao board, as well as producing relevant documentation for IDEAS. Being a mixed-signal general purpose board, effort has been made to include a high number of features and connectivity options: Galao holds specialized analog circuits for receiving differential signals, transmitting fast pulses of adjustable amplitude, registering trigger signals for readout synchronization as well as containing a broad assortment of both voltage and current bias generators. On the digital side, a System on Module solution has been incorporated, serving as a control unit for all the analog circuitry while providing a large amount of digital I/Os. The board has been made so that it may be accessed through Ethernet, USB and JTAG interfaces. Furthermore, the Galao board has several power rails, both for the analog and digital domain, with the PCB designed so that digital switching has a minimal impact the analog signals. The Galao board was finally produced, allowing for some initial testing. The results of the conducted tests are positive, as the board powers up and is operational with its digital logic being fully controllable. Some faults in the schematic have been discovered after the manufacturing of the Galao board, but these have all been readily fixable. The board is hence in a working condition, and ready to be interfaced towards an ASIC with an ASIC test board that is to be designed.

• By, Mathias; Kile, Eirik & Aunet, Snorre (2015). FPGA Implementation and Evaluation of a Genetic Algorithm for Digital Adaptive Nulling using Space-Time Adaptive Processing. NTNU. Show summary

  The thesis is done in cooperation with Kongsberg Defence Systems.

• Skjølsvik, Hallstein; Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2015). Ultra low voltage combinatorial logic building blocks. NTNU.

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