Snorre Aunet

• Kalajdzic, Marko & Aunet, Snorre (2026). A Low-Power, Ultra-Low-Voltage Custom Topology CMOS Inverter Applicable Across All Regions of Operation. IEEE Access. 14, p. 141896–141907. doi: 10.1109/access.2026.3732994. Full text in Research Archive Show summary

  This paper proposes a custom topology (CT) ultra-low-voltage (ULV) inverting amplifier that extends well-known ULV topologies via a dynamically conducting complementary arrangement, potentially improving robustness towards process variations over 6T Schmitt trigger (ST) inverters while reducing power. Post-layout 22 nm FDSOI implementations (small Lg=20  nm, large Lg=130  nm) are matched to equal active area to isolate topology effects and simulated over 0-70° C, process corners, and Monte Carlo (process+mismatch) with VDD sweeps (130-900 mV small, 100-900 mV large). In 3-stage ring oscillators, CT reduces average power by 32-48% (small) and 42-50% (large) across the full supply range versus ST, with frequency changes of −42 to −19% (small) and −19 to + 3% (large), energy per switching is reduced by up to 18% (small) and 44% (large). Simulation-based voltage transfer characteristics, static noise margin, and Monte Carlo switching-point/gain analyses indicate increased robustness, establishing CT as a potential power-efficient, process-resilient ULV standard-cell alternative to ST inverters, provided a mismatch-aware sizing strategy.

• Khalid, Muhammad Umer; Ytterdal, Trond & Aunet, Snorre (2026). A Sub-70-mV SRAM Based on DTMOS Schmitt-Trigger Circuits in 130-nm SOI CMOS for Self-Powered IoT. IEEE Access. 14, p. 113511–113530. doi: 10.1109/ACCESS.2026.3715921. Full text in Research Archive
• Su, Shengkai & Aunet, Snorre (2026). Self-Oscillating Joule Thief Converters for MEMS Electromagnetic Energy Harvesting: Analytical Modeling and Experimental Validation. IEEE transactions on industrial electronics (1982. Print). ISSN 0278-0046. doi: 10.1109/TIE.2026.3663767. Full text in Research Archive
• Moulin, Kaspar Sigurd; Lande, Tor Sverre; Aunet, Snorre & Wisland, Dag Trygve Eckhoff (2026). Efficient Asynchronous Sampling of Ripple Counter in VCO-ADC Using Ripple Register and Event Arbitration. IEEE Transactions on Circuits and Systems - II - Express Briefs. ISSN 1549-7747. 73(2), p. 138–142. doi: https:/ieeexplore.ieee.org/document/11339947. Full text in Research Archive Show summary

  We present a power and area-efficient solution for robust asynchronous sampling of a ripple counter for coarse-fine VCO-ADCs. We show that by replacing the parallel register with a delay-matched sequential register and utilizing asynchronous arbitration, sampling errors are avoided. Post-layout simulation of a 7-bit system shows that our proposed solution tolerates VCO frequencies <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$197\times $ </tex-math></inline-formula> higher than the baseline design, while requiring a 42 % increase in power and a 26 % area overhead, thereby improving upon a state-of-the-art double-counter solution.

• Roland, Markus Heyerdahl; Aunet, Snorre & Yakovlev, Alexandre (2025). Faster Training of Tsetlin Machines With Deterministic Multi-Step Automata. In Lei, Jiao & Shafik, Rishad Ahmed (Ed.), Tsetlin Machine (ISTM), International Symposium on the. IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798331569228. p. 48–55. doi: 10.1109/ISTM67926.2025.00016. Full text in Research Archive Show summary

  This article investigates the use of "multi-step variable structure finite-state" automata (MVFA) in place of Tsetlin automata (TA) for a software implementation of the coalesced Tsetlin machine (CoTM) with up to 2048 clauses for classification of the MNIST dataset. The use of deterministic MVFA compared to TA resulted in a harmonic mean speedup of 5.6 times for training time per epoch and a mean increase in accuracy of 0.23% over the last 10 out of 50 epochs of training for the model sizes investigated. For CoTM with 1024 clauses, it was here observed that TA requires a minimum of 7 bits of state to obtain maximal first epoch accuracy, while MVFA requires a minimum of 10–12 bits. In light of previous work on MVFA, the findings presented here points to that the optimal choice of stochastic vs. deterministic automata depends on characteristics of the dataset.

• Nägle, Louisa Charlotte; Aunet, Snorre & Rückert, Ulrich (2025). Exploiting Multi-VT FDSOI Technology for Improved Area and Energy Trade-Offs for Ultra-Low Voltage Schmitt Triggers. In Nurmi, Jari; Aunet, Snorre & Saberkari, Alireza (Ed.), 2025 IEEE Nordic Circuits and Systems Conference (NorCAS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798331515010. p. 1–7. doi: 10.1109/NorCAS66540.2025.11231312. Full text in Research Archive Show summary

  This work presents the design and comparison of three Schmitt Trigger inverter implementations, optimized for ultra-low-voltage operation down towards 100mV, targeting energy-constrained applications such as IoT sensor nodes and biomedical interfaces. The commercial 22nm FD-SOI (22FDX) process by GlobalFoundries is used. The impact of transistor threshold voltage type selection and sizing on performance, energy efficiency, and layout area is investigated. Device characteristics of NMOS and PMOS variants were analyzed to enable combinations with decreased area. The inverters were evaluated using DC analysis and as ring oscillators in transient analysis to extract propagation delay, power, and energy down to 100mV. The results demonstrate that carefully pairing low- and regular threshold devices (multi-VT) allows for favorable tradeoffs between speed and leakage, with minimum energy points occurring in the subthreshold region. With approximately twice the propagation delay and one-eighth the power consumption, the energy and total area are approximately four times less than those of the reference Schmitt Trigger inverter. Their robust functionality at ultra-low supply voltages makes them promising building blocks for future subthreshold and energy-harvesting systems.

• Khalid, Muhammad Umer; Ytterdal, Trond & Aunet, Snorre (2025). Comparative Analysis of Full Adders Based on DTMOS Schmitt-Trigger Standard Cells Operating at Sub-100 mV Supply Voltage. In editors, IEEE (Eds.), 2025 40th Conference on Design of Circuits and Integrated Systems (DCIS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798331580919. p. 182–187. doi: 10.1109/dcis67520.2025.11281931. Full text in Research Archive
• Khalid, Muhammad Umer; Ytterdal, Trond & Aunet, Snorre (2025). Robust DTMOS Schmitt-Trigger Circuits in 130 nm SOI CMOS for Sub-100mV Supply Voltage. In editors, IEEE (Eds.), 2025 40th Conference on Design of Circuits and Integrated Systems (DCIS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798331580919. doi: 10.1109/dcis67520.2025.11281895. Full text in Research Archive
• Khalid, Muhammad Umer; Ytterdal, Trond & Aunet, Snorre (2025). DTMOS Schmitt-Trigger Standard Cells based Frequency Divider Operating at 60 mV. In editors, IEEE (Eds.), 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798331503901. doi: 10.1109/prime66228.2025.11203731. Full text in Research Archive
• Su, Shengkai; Truong, Binh Duc; Aunet, Snorre & Le, Phu Cuong (2024). A Versatile MEMS Electrostatic Transducer Structure To Achieve Near-Zero Stiffness For Low-Frequency Energy Harvesting. In Halvorsen, Einar (Eds.), 2024 IEEE 23rd International Conference on Micro and Miniature Power Systems, Self-Powered Sensors and Energy Autonomous Devices (PowerMEMS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798350380200. p. 260–263. doi: 10.1109/PowerMEMS63147.2024.10814244. Full text in Research Archive Show summary

  This paper presents an inertial structure with electrically controllable stiffness, enabling adaptive low-frequency operation in vibration-based MEMS energy harvesters. The structure design combines bistable and linear springs with different electrostatic transducers to maintain overall stiffness to close or equal to zero over the operational range of proof mass displacement. In the zero-stiffness mode, the simulation results show that a maximum displacement amplitude can be achieved within a low-frequency range of f≤14 Hz, even when excited by an extremely small acceleration of A=5×10^{−3}g. As an added feature, the harvester can be adjusted to operate in either linear or bistable mode by tuning the linear electromechanical forces of the integrated transducers. Multimode operation of the proposed structure can offer a versatile solution that effectively adapts to the diverse frequency characteristics of real-world ambient vibrations.

• Amble, Magnus; Aunet, Snorre; Wisland, Dag Trygve Eckhoff & Kjelgård, Kristian Gjertsen (2023). Randomized Bulk-Voltages: A Countermeasure to Mask Side-Channel Leakage of CMOS Logic Gates. In Setti, Gianluca & Manganaro, M. (Ed.), Proceedings,2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798350302103. p. 708–712. doi: 10.1109/MWSCAS57524.2023.10406067. Full text in Research Archive
• Seyedi, Azam; Aunet, Snorre & Kjeldsberg, Per Gunnar (2022). Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications with High Reliability Requirements. IEEE Access. 10, p. 30624–30642. doi: 10.1109/ACCESS.2022.3157402. Full text in Research Archive
• Su, Shengkai; Truong, Binh Duc; Aunet, Snorre & Le, Phu Cuong (2021). A reliable and wide-range tuning technique for low-frequency MEMS energy harvesters. In Jia, Yu (Eds.), Proceedings, 2021 IEEE 20th International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781665422185. doi: 10.1109/PowerMEMS54003.2021.9658410. Full text in Research Archive Show summary

  A frequency-tuning method with a high tuning sensitivity is difficult to control precisely or even cause the pull-in phenomenon before attaining the desired frequency. Here, the sensitivity is defined by the rate of change of the frequency with respect to the bias voltage. In this paper, a two-stage tuning technique is proposed to overcome fundamental challenges of MEMS vibration energy harvesting from low-frequency applications. The technique can significantly reduce the tuning sensitivity in comparison with previous tuning methods. In our particular example designs, when the frequency is tuned from 1 kHz to 50 Hz, a traditional tuning approach has a sensitivity of 495 Hz/V, while that of the proposed tuning approach is 18 Hz/V under the same design constraint. The effects of the tip capacitance are taken into account when investigating the pull-in phenomenon and estimating the theoretical lowest tunable frequency. The findings can provide a further guideline towards the optimal design of MEMS vibration energy harvesters operating at low-frequency ranges.

• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2021). Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider Applications. In Nurmi, Jari; Wisland, Dag Trygve Eckhoff; Aunet, Snorre & Kjelgård, Kristian Gjertsen (Ed.), Proceedings, 2021 IEEE Nordic Circuits and Systems Conference (NORCAS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781665407120. doi: 10.1109/NorCAS53631.2021.9599871. Full text in Research Archive Show summary

  Abstract—This study aims at comparing two subthreshold flipflop architectures in frequency divider applications, implemented and fabricated in 130 nm CMOS process technology. They are the Power PC (Performance Computing) and Nand race-free flipflops. Identification of a reliable and power efficient flip-flop, used in a frequency divider for ultra-low supply voltages, has been verified by measurements. The simulated results based on a netlist extracted from layout show that upsizing the Power PC flip-flop increases it’s reliability while it may still provide lower power consumption than the Nand race-free flip-flop. Based on results verified by measurements for ten chip samples, both frequency dividers have demonstrated functionality down to a Vdd of 135 mV. The Power PC flip-flop based frequency divider is 24% more energy efficient than the Nand race-free counterpart at an ultra-low supply voltage of 160 mV. The energy per operation for the Power PC- and Nand race-free- frequency dividers at the minimum energy point (MEP) of 250 mV, and maximum operating frequency, are 12.2 and 12.5 fJ, respectively

• Aunet, Snorre (2021). Ultra Low Voltage Sub-100 mV Vdd CMOS. In Gauberts, Jean & Barragan, Manuel (Ed.), Proceedings, 19th IEEE Northeast Workshop on Circuits and Systems (NEWCAS), 2021. IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781665424295. doi: 10.1109/NEWCAS50681.2021.9462735. Full text in Research Archive Show summary

  Abstract—Logic and memory proven in silicon, operating at sub-100 mV Vdds are discussed. Static CMOS is likely to be augmented with Schmitt-trigger based solutions, especially for memories that should operate at Vdds below 100 mV.

• Yassin, Yahya Hussain; Jahre, Magnus; Kjeldsberg, Per Gunnar; Aunet, Snorre & Catthoor, Francky (2021). Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode. Journal of Signal Processing Systems. ISSN 1939-8018. 93(1), p. 33–48. doi: 10.1007/s11265-020-01544-z. Full text in Research Archive Show summary

  Stringent power budgets in battery powered platforms have led to the development of energy saving techniques such as Dynamic Voltage and Frequency scaling (DVFS). For embedded system designers to be able to ripe the benefits of these techniques, support for efficient design space exploration must be available in system level simulators. The advent of the edge computing paradigm, with power constraints in the mW domain, has rendered this even more essential. Without a fast and accurate methodology for architecture simulation and energy estimation, the benefit of new ideas and solutions cannot be evaluated. In this paper, we propose a non-intrusive application controlled DVFS management implementation in the GEM5 simulator, used with GEM5’s system call emulation mode. We also propose a novel architecture independent energy model based on categorization of different measurable workload classes. Our energy model is parametrized and calibrated with power measurements on a SAM4L microcontroller board, containing an ARM Cortex M4 processor. Together with the GEM5 output statistics, the model accurately estimates the total energy consumption of our simulated system. The results from our modified GEM5 simulator are validated with representative signal processing applications. After correction of systematic offset errors, our results deviate with less than 4% compared to measurements from the SAM4L microcontroller. Our contributions in this paper can easily be tailored to other processor models in GEM5 and to future versions of GEM5. It will therefore enable system architects to explore new techniques and compare the improvements relative to existing architectures.

• Låte, Even; Ytterdal, Trond & Aunet, Snorre (2020). An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V. IEEE Transactions on Circuits and Systems - II - Express Briefs. ISSN 1549-7747. 67(11). doi: 10.1109/TCSII.2020.2966654. Full text in Research Archive Show summary

  We propose architectural advances in low voltage, energy efficient, level shifters. A write assist circuit is introduced,to support up-conversion of deep subthreshold inputs. We also present an approach to reduce the leakage current in split signal output stages. A prototype was created in a 130 nm bulk CMOS process, and some samples were successfully tested for input voltages as low as 5 mV. For 10 measured samples, the mean functional, minimum, input voltage was 31.1 mV. By applying body bias to selected NMOS transistors to compensate for process and mismatch variation, the measured mean minimum input voltage was lowered to 14.3 mV. The leakage reduction in the split control output driver reduces the driver leakage by a factor of 8. The designed level shifter was found to be energy efficient compared to published structures, it consumed an average of 25.9 fJ per conversion in post-layout simulations and the delay was measured to 21.08 ns at 300 mV input signals.

• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology. In IEEE, . (Eds.), 2020 IEEE Nordic Circuits and Systems Conference (NorCAS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781728192260. doi: 10.1109/NorCAS51424.2020.9265001. Full text in Research Archive Show summary

  This study presents a comparative study of single, regular and flip well subthreshold SRAMs in 22 nm FDSOI technology. A 7T loadless SRAM cell with a decoupled read and write port has been used as a case study. Simulation results, based on the extracted netlist from layout, show that the speed of the flip well SRAM is significantly better than that of the single and regular well SRAMs. In terms of leakage current, single well is the best option. The regular well type has lower static noise margin (SNM) variability. Among all devices used (HVT, RVT, LVT and, SLVT) available in a commercially available 22 nm FDSOI technology, the best combination for minimizing energy per access is HVT devices as driver transistors and RVT for the rest of the transistors. This study may help designers to select an optimal architecture based on their application and performance requirements. The 22 nm FDSOI technology enables a wide range of back gate bias voltages to improve the read stability and write ability of the SRAMs and, hence, their minimum operating voltage and power consumption.

• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders. In IEEE, . (Eds.), 2020 IEEE Nordic Circuits and Systems Conference (NorCAS). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781728192260. doi: 10.1109/NorCAS51424.2020.9265131. Full text in Research Archive Show summary

  This paper designs and reports energy efficient subthreshold adders using 22 nm FDSOI technology. The dynamic body biasing technique and multi-threshold voltage devices have been used to match Pull up/Pull down networks (PUN/PDN). The post-layout simulation results show that the logic gates and full adder circuit based on dynamic body biasing are more robust than those with conventional body bias against process, voltage, and temperature (PVT) variations at ultra low supply voltages. The adder based on the conventional and dynamic body biasing techniques have achieved energy per addition of 0.23 fJ at Vdd =300 mV and 0.56 fJ at Vdd =140 mV, respectively. Compared to the other published subthreshold adders in [1] and [2], the energy per addition for our designed adders improved by 2.82X, 28.1X, respectively. The minimum operating supply voltage for dynamic and conventional body bias adders based on Monte Carlo simulations taking into account both mismatch and process variations are 140 and 200 mV, respectively. The area for conventional body biased adder has been reduced by 43.9 and 38.8 percent compared to those of the adders in [1] and [3], respectively.

• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). An ultra low voltage subthreshold standard cell based memories for IoT applications. In Seyedarabi, Hadi (Eds.), Proceedings, 28th Iranian Conference on Electrical Engineering. IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781728172965. doi: 10.1109/ICEE50131.2020.9260950. Full text in Research Archive Show summary

  In this paper, we have designed an ultra low voltage standard cell based memory (SCM) in the subthreshold domain. The SCM has been synthesized, placed and routed based on an ultra low voltage full custom standard cell library using 130 nm process technology, functional for subthreshold supply voltages as low as 140 mV, which is well below the supply voltages reported in the previous works of SCMs. This SCM has been designed based on the standard D-latch which holds data at a supply voltage as low as 170 mV. The designed SCM is functional for a temperature range of 27–50 °C applicable for implantable biomedical systems requiring small memory capacity. According to the simulations from the extracted netlist, the energy per bit access at Vdd=200 mV and 333 kHz frequency, suitable for many loT applications, is 1.54 fJ.

• Låte, Even; Ytterdal, Trond & Aunet, Snorre (2020). Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping. IEEE Transactions on Very Large Scale Integration (vlsi) Systems. ISSN 1063-8210. 28(10), p. 2223–2227. doi: 10.1109/TVLSI.2020.3013139. Full text in Research Archive Show summary

  This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally flipped during write operations to reach the more beneficial state for storage. A 1-kb SRAM block of low-voltage memory cells was implemented and manufactured in a 130-nm CMOS. The memory cells were made writable and read-stable at low supply voltages with a single-ended write and single-ended read structure using six multithreshold transistors that give rise to an asymmetric retention power. At a supply voltage of 350 mV, the content-dependent leakage power in the asymmetric memory cell is 23 times smaller when storing logic “1”s compared with logic “0”s. A derived statistical model suggests that the mean, wordwise, static power savings of the word-flipping scheme become 15.70% for 8-bit words of uniform bit probability. For the implemented SRAM macro, the mean improvement for the retention power is, including flip logic and decoder and driver overheads, found to be 14.69%. In boundary tests, by writing all words full of undesired values, the power saving becomes 80.37%, while writing all words full of desired values causes a power penalty of 6.14%. Measurement results confirm the improvement in retention power with a ten-chip mean improvement of 11.93% for the same data set.

• Christensen, Steinar Thune; Aunet, Snorre & Qadir, Omer (2019). A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural Networks. In Nurmi, Jari; Ellervee, Peeter; Halonen, Kari & Røning, Juha (Ed.), 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781728127699. doi: 10.1109/NORCHIP.2019.8906950. Full text in Research Archive Show summary

  This paper presents a configurable, versatile and flexible architecture for hardware acceleration of convolutional neural networks (CNNs) that is based on storing and accumulating entire feature maps in local memory inside the accelerator. This has been done while aiming to be able to process any type of CNN while consuming as low power as possible and achieving the highest possible energy efficiency. Energy efficiency refers to the number of operations per unit energy (measured in Multiply-Accumulate operations per unit energy, MACs/s/W or MACs/J). Mainly, two different versions of the architecture have been synthesized and tested using different configurations of hardware parameters. It performs well when compared to the state-of-the-art, achieving an improved energy efficiency of over a factor 5 for select CNN layers. The most energy efficient configuration achieves 175 GMACs/s/W, while consuming 2.3 mW of power and occupying 585 KGEs (Kilo Gate Equivalents) of area at 1V supply voltage and a clock frequency of 100MHz.

• Seyedi, Azam; Aunet, Snorre & Kjeldsberg, Per Gunnar (2019). Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications. In Nurmi, Jari; Ellervee, Peeter; Halonen, Kari & Røning, Juha (Ed.), 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781728127699. doi: 10.1109/NORCHIP.2019.8906911. Full text in Research Archive Show summary

  In the electronics space industry, memory cells are one of the main concerns, especially in term of reliability, since radiation particles may hit cell nodes and disturb the state of the cell, possibly causing fatal errors. In this paper we propose the Nwise SRAM cell, an area-efficient and highly reliable radiation hardened memory cell for use in high-density memories for space applications. Simulations confirm that the proposed Nwise cell is fully tolerant to single event upsets (SEU) in any one of its nodes regardless of upset polarity. Meanwhile, compared with the RHBD-10T cell, the latest area-efficient radiation hardened memory cell, it has higher robustness: the minimum critical charge of Nwise is 4.1× higher than the minimum critical charge of the RHBD-10T cell. It also shows 23% and 12% improvements in read and write static noise margin (SNM). Furthermore, compared with RHBD-10T, up to 18.4% and 7.0% power savings are obtainable during write and read operations respectively. Nwise is about 2.28× faster than RHBD-10T during the more frequent read operation, with a similar penalty in write time. Finally, Nwise is the first proposed high density and reliable radiation hardened memory cell that has been designed using the 28nm FD-SOI technology node. Index Terms—space applications, radiation hardening, single event upset (SEU), multiple event upset (MEU), SRAM design, 28nm FD-SOI, reliability, soft errors, Nwise cell

• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2019). Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology. In Nurmi, Jari; Ellervee, Peeter; Halonen, Kari & Røning, Juha (Ed.), 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781728127699. doi: 10.1109/NORCHIP.2019.8906939. Full text in Research Archive Show summary

  Abstract—This study presents a strategy to determine optimal body bias voltages for ultra low voltage digital circuits in the 22 nm Fully Depleted Silicon On Insulator Technology (FDSOI). The efficiency of body biasing for achieving high functional yield has been investigated by using reveres back bias voltages for HVT devices. The strategy has been evaluated through the design of an ultra low voltage Xor based adder at supply voltages varying from 140-160 mV and temperature range 27-50 °C at 1 kHz frequency. The adder under optimal body bias consumes 4.67 percent less energy than zero body bias at Vdd=150 mV and frequency of 1 kHz. The adder is fully functional functional for 1 k Monte Carlo simulations at optimal back bias voltage. The yield has improved by 0.4 percent in optimal back bias voltage compared to zero body bias. The results show the lowest Energy per cycle, variability and high functional yield for the obtained optimal body bias voltage. Also, additional analysis confirm the dependency of optimal body bias voltage on the switching activity and operating conditions for a given technology. We also show that the relative energy variability is larger than the delay variability over the back bias voltage range. Index Terms—optimal body bias, reverse back bias, HVT device, activity factor, variability, functional yield.

• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2019). Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder. In Nurmi, Jari; Ellervee, Peeter; Halonen, Kari & Røning, Juha (Ed.), 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781728127699. doi: 10.1109/NORCHIP.2019.8906917. Full text in Research Archive Show summary

  Abstract—In this study, 8, 16 and 32 bits ultra low power, robust, Kogge Stone (KSA) and Ripple Carry (RCA) adders using available 130 nm CMOS bulk technology have been designed and analyzed at subthreshold supply voltages ranging from 140-160 mV and temperature range of 27-50 °C at 5 kHz frequency for implantable biomedical devices. Simulation results based on netlists extracted from layout confirm that with a marginal increase in the supply voltage of the RCA compared to that of the KSA adder at the same speed, the power consumption and energy per operation, as well as the area usage of the RCA is far less than KSA. For example, when increasing the supply voltage of the 8 bit RCA by 44 mV compared to that of the KSA adder, the energy per operation for the KSA is about 3.5 times higher than that of the RCA. We have investigated different RCA topologies and considered the minimum energy point varies with different topologies. In addition, in the case of low throughput applications, using the stacked inverters for the full adder will reduce the leakage current and the total energy per cycle of the circuit. For the Minority-3 based 32 bits RCA with stacked inverters, the energy per cycle improves 15 percent compared to that of Minority-3 based 32 bits RCA at Vdd = 150 mV. Index Terms—KSA, RCA, ultra low voltage, implantable biomedical devices, channel length upsizing, minimum energy point, stacked inverters.

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• Nurmi, Jari; Aunet, Snorre & Saberkari, Alireza (2025). 2025 IEEE Nordic Circuits and Systems Conference (NorCAS). IEEE (Institute of Electrical and Electronics Engineers). ISBN 9798331515010. 400 p. Full text in Research Archive
• Nurmi, Jari; Wisland, Dag Trygve Eckhoff; Aunet, Snorre & Kjelgård, Kristian Gjertsen (2021). Proceedings, 2021 IEEE Nordic Circuits and Systems Conference (NORCAS). IEEE (Institute of Electrical and Electronics Engineers). ISBN 9781665407120. 220 p. Full text in Research Archive
• Nurmi, Jari; Wisland, Dag T; Aunet, Snorre & Kjelgård, Kristian Gjertsen (2020). Proceedings, Sixth IEEE Nordic Circuits and Systems Conference (NorCAS 2020). IEEE (Institute of Electrical and Electronics Engineers). ISBN 9781728192260. 205 p. Full text in Research Archive Show summary

  On behalf of the Organizing Committee, we would like to welcome all of you to the Sixth IEEE Nordic Circuits and Systems Conference (NorCAS 2020). The conference is a merge of the well-established conferences NORCHIP and the International Symposium on System-on-Chip (SoC). We have a high-quality program with keynotes and papers to be presented. Research covering a wide range of topics within circuits and systems in the digital, analog and mixed domains will be presented. From in total 58 papers submitted, 29 papers were selected for oral presentation in the virtual conference, yielding exactly 50% acceptance rate. There will be four invited speakers who will share their view on emerging key technologies in the circuits and systems field. In the opening session Prof. An-Yeu (Andy) Wu from National Taiwan University will discuss compressive sensing and compressive analytics. Later in the afternoon Prof. Alberto Bosio from ICL, France, will give insights to approximate computing and, in particular, testing of it. In the second morning, Prof. Tim Constandinou from University College London, UK, will present his talk on “Future Human: Merging Minds and Machines.“ The final talk is given by Prof. Alexander Wyglinsky from Worchester Polytechnic Institute, USA, introducing an educational view to Software-Defined Radio. We would like to forward great thanks to IEEE Circuits and Systems Society (CAS) for financial co-sponsoring of the conference. Thanks also to Tampere University and University of Oslo for the efforts on the congress office and virtual platform. We are also thankful to all the Program Committee members and reviewers who have put time and effort into reviewing the submitted papers. Moreover, we are grateful to the NorCAS steering committee for helpful advice and their contribution in the paper selection process. We hope that you will enjoy your time in the virtual conference. We wish you an inspiring conference where your knowledge is increased and friendships are both established and strengthened.

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• Aunet, Snorre (2026). Applied Partner Theme 1 (“APT1”) Battery-less AI-capable IoT nodes. Full text in Research Archive Show summary

  presentation of objectives related to Applied partner theme 1 related to SFI NICE https://www.ntnu.edu/nice

• Aunet, Snorre (2026). CC-Norchip (parts of European Chips Act) – a few words. Full text in Research Archive
• Nurmi, Jari; Aunet, Snorre & Saberkari, Alireza (2025). Guest Editorial: Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2024. IEEE Transactions on Very Large Scale Integration (vlsi) Systems. ISSN 1063-8210. 33(11), p. 2903–2906. doi: https:/ieeexplore.ieee.org/document/11222395. Full text in Research Archive
• Nägle, Louisa Charlotte; Klarhorst, Christian; Hagemeyer, Jens; Aunet, Snorre & Rückert, Ulrich (2025). Subthreshold Operation with Schmitt Trigger Logic: Designing 100 mV Standard Cells in 22 nm FDSOI. In Gerfers, Friedel & Scholz, Philipp (Ed.), proceedings Analog Workshop 2025. Universitätsverlag der TU Berlin. p. 12–16. doi: https:/www.static.tu.berlin/fileadmin/www/10002215/Analog_Workshop/AnalogWorkshop2025_Program.pdf. Full text in Research Archive Show summary

  Subthreshold (SubVT) operation is a promising technique to enable low-power digital circuits at very low supply voltages. However, its usage is hindered by degraded switching behavior due to a low on/off-current ratio. This paper investigates the use of Schmitt Trigger (ST) logic to design SubVT standard cells in a 22 nm FDSOI process, targeting a supply voltage as low as 100 mV. A set of ST-based standard cells, including NOT, NAND, and NOR gates, was designed, simulated, and characterized. To evaluate the performance of the proposed cells, a 2-bit multiplier was synthesized using both conventional CMOS and the developed ST-based SubVT cells. Initial results indicate the feasibility of operating these cells at the target supply voltage. They show the necessary robustness against process, voltage, and temperature variations at the cost of increased transistor count and area. The presented library operates at around 100 mV VDD and has a propagation delay that is 106 times larger, a power consumption that is 103 times lower, and an energy consumption that is 103 times larger compared to a conventional CMOS library that operates at 800 mV. These findings highlight the potential of combining ST logic with SubVT operation for ultra-low-power digital systems, particularly where robustness and minimal supply voltages are prioritized over speed and area.

• Aunet, Snorre (2025). WP2 Fascilitating acces to capacities - contents, plans, deliverables. Full text in Research Archive
• Nägle, Louisa Charlotte; Klarhorst, Christian; Hagemeyer, Jens; Aunet, Snorre & Rückert, Ulrich (2025). Open subthreshold standard cell library for energy-efficient digital circuits. doi: https:/wiki.f-si.org/images/archive/a/a1/20250701064607!OpenSubVTLib_lnaegle_2.pdf. Full text in Research Archive
• Aunet, Snorre (2024). Application Specific Integrated Circuits - making the world even greener". Full text in Research Archive
• Su, Shengkai; Truong, Binh Duc; Aunet, Snorre & Le, Phu Cuong (2024). A Versatile MEMS Electrostatic Transducer Structure To Achieve Near-Zero Stiffness For Low-Frequency Energy Harvesting. Full text in Research Archive Show summary

  This paper presents an inertial structure with electrically controllable stiffness, enabling adaptive low-frequency operation in vibration-based MEMS energy harvesters. The structure design combines bistable and linear springs with different electrostatic transducers to maintain overall stiffness to close or equal to zero over the operational range of proof mass displacement. In the zero-stiffness mode, the simulation results show that a maximum displacement amplitude can be achieved within a low-frequency range of f≤14 Hz, even when excited by an extremely small acceleration of A=5×10−3 g. As an added feature, the harvester can be adjusted to operate in either linear or bistable mode by tuning the linear electromechanical forces of the integrated transducers. Multimode operation of the proposed structure can offer a versatile solution that effectively adapts to the diverse frequency characteristics of real-world ambient vibrations.

• Nurmi, Jari; Aunet, Snorre & Saberkari, Alireza (2024). Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2023. IEEE Transactions on Very Large Scale Integration (vlsi) Systems. ISSN 1063-8210. 32(12), p. 2169–2172. doi: 10.1109/TVLSI.2024.3493512. Full text in Research Archive
• Aunet, Snorre (2024). European Chips Act. Full text in Research Archive
• Nurmi, Jari; Aunet, Snorre & Saberkari, Alireza (2023). Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2022. IEEE Transactions on Very Large Scale Integration (vlsi) Systems. ISSN 1063-8210. 32(1), p. 1–3. doi: 10.1109/TVLSI.2023.3339268. Full text in Research Archive
• Djupdal, Asbjørn; Själander, Hans Magnus; Jahre, Magnus & Aunet, Snorre (2023). Minimizing the Energy Usage of Tiny RISC-V Cores. Full text in Research Archive
• Aunet, Snorre (2023). Ultra low voltage --/ low power technologies and building blocks for full custom integrated circuits - What ?, Why ?, How ?, Goals? Full text in Research Archive
• Amble, Magnus; Aunet, Snorre; Wisland, Dag Trygve Eckhoff & Kjelgård, Kristian Gjertsen (2023). Randomized Bulk-Voltages: A Countermeasure to Mask Side-Channel Leakage of CMOS Logic Gates. Full text in Research Archive
• Aunet, Snorre (2022). Towards Sub-100 mV CMOS. Full text in Research Archive
• Aunet, Snorre (2021). Ørsmå energihøstende IoT-noder. Full text in Research Archive
• Su, Shengkai; Truong, Binh Duc; Aunet, Snorre & Le, Phu Cuong (2021). A reliable and wide-range tuning technique for low-frequency MEMS energy harvesters. Full text in Research Archive
• Aunet, Snorre & Aunet, Snorre (2021). Ultra Low Voltage Sub-100 mV Vdd CMOS. Full text in Research Archive
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2021). Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider Applications. Full text in Research Archive
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). 0 Comparative Study of Single, Regular and Flip well Subthreshold SRAMs in 22 nm FDSOI Technology. Full text in Research Archive
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). An ultra low voltage subthreshold standard cell based memories for IoT applications. Full text in Research Archive
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2020). 0 Multi-threshold voltage and dynamic body biasing techniques for energy efficient ultra low voltage subthreshold adders. Full text in Research Archive
• Seyedi, Azam; Aunet, Snorre & Kjeldsberg, Per Gunnar (2019). Towards Compact Radiation Hardened Memories for Space Applications. Full text in Research Archive
• Aunet, Snorre (2019). Asynchronous ultra low voltage / low power CMOS - what and why, but not much about how. Full text in Research Archive Show summary

  Reducing the supply voltage to the subthreshold region, where the supply voltage is below the absolute values of the inherent threshold voltages, has been regarded the most direct and dramatic means of reducing overall power consumption. Full Custom logic and memory building blocks are needed to take full advantage of subthreshold operation, that may reduce power consumption by orders of magnitude, and energy per operation by typically 10 times or more, compared to normal super-threshold circuits. The lower the supply voltage, the lower the power consumption. Examples of a 32-bit RISC processor operating at subthreshold voltages, as well as arithmetic building blocks operating at supply voltages below 100 mV are mentioned briefly. The strong relationships between supply voltage and power consumption, as well as energy per operation, are due to several exponential relationships between voltages across nodes of the transistor, temperature and threshold voltages, in subthreshold operation. Dealing with process-, voltage-, and temperature (“PVT”-) variations is the greatest challenge when exploiting subthreshold techniques for ultra low power / low energy circuits. Circuit delays can vary by up to orders of magnitude, due to PVT variations. When the traditional synchronous circuits design paradigm is used, combined with subthreshold operation, necessary worst-case timing considerations leads to slowing down circuitry by up to orders of magntitude, while at the same time increasing power- and energy consumption radically, compared to superthreshold / strong inversion circuits. To fully exploit the low power / low energy potential of subthreshold circuits, asynchronous solutions not taking worst case behavior into account in the normal fashion, may be a key concept.

• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2019). Ultra low voltage subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder. Full text in Research Archive
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2019). Low Energy CMOS building blocks for IoT. Full text in Research Archive
• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2019). Low Energy CMOS building blocks for IoT. Full text in Research Archive
• Støle, Martin Mathias; Næss, Torbjørn & Aunet, Snorre (2024). "RISC-V P extension implementation". Norges Teknisk Naturvitenskapelige Universitet. Full text in Research Archive
• Rusten, Siri Westgård; Qadir, Omer & Aunet, Snorre (2024). «Design, compare and analyze various synchronisers from the async community». NTNU. Full text in Research Archive
• Bjørklund, Eirik Ekrheim; Skjermo, Tor Øistein & Aunet, Snorre (2024). Rogowski Coil Current Sensor Wireless Battery Powered. NTNU. Full text in Research Archive
• Hassan, Muhammad Zain Ul; Abrahamsen, Henrik Skarre; Lindholm, Victor; Hagen, Anders Ivar & Aunet, Snorre (2024). FPGA based Hybrid Stepper Motor Control. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Hybrid trinnmotorer er mye brukt i automasjonsindustrien på grunn av deres pålitelighet og presisjon som oppnås gjennom de kontrollerte diskrete trinnene. I denne oppgaven presenteres en implementering av stepper motor control i Artix-7 Field Programmable Gate Arrays (FPGA) ved bruk av forskjellige kontrollalgoritmer som full stepping, half stepping og micro stepping. Implementering viste at det halve trinnet produserer mindre dreiemoment og mindre mekanisk støy sammenlignet med fulltrinnsoperasjonen. For å kompensere for tilbake-emf ble strømtilnærming for forskjellige hastigheter brukt for effektiv åpen sløyfekontroll som viste god ytelse under konstante belastningsforhold. Studien viste at den samme strømtilnærmingen kan brukes for halvt og fullt trinn uten å kompromittere ytelsen, men en annen strategi er nødvendig for mikrosteppingen, da implementering av mikrostepping under samme strømtilnærming resulterte i mer støy enn halv- og helstegsdrift. Kontrollstrategi med lukket sløyfe ved bruk av posisjonsfeedback og en sinusformet kommutasjonsalgoritme ble implementert. FPGAs evne til pålitelig å kontrollere trinnmotoren samtidig som nøyaktigheten ble validert gjennom maskinvareimplementering. I tillegg, for en jevnere operasjon, ble S-kurvebevegelsesprofilalgoritmen implementert. Resultatene viser imidlertid at S-kurven kan være svært ressurskrevende hvis den implementeres med presisjon. Noen måter å optimalisere ressursene på ble diskutert og resultatene viste mindre forbedringer i ressursutnyttelsen. Imidlertid, hvis kontrollalgoritmen er implementert uten bevegelsesprofilen, har Aritx-7-brikken nok ressurser til å kjøre 4 trinnmotorer parallelt med uavhengige kontroller. Denne oppgaven understreker FPGAs allsidige natur når det gjelder å implementere avanserte kontrollalgoritmer for trinnmotorer, og gi en vei videre for forbedrede løsninger i ulike industrielle applikasjoner.

• Bakke, Andreas Sandsmark; Aunet, Snorre & Henninen, Svein Rypdal (2024). Design of a RISC-V Floating Point Unit Model. Norges Teknisk Naturvitenskapelige Universitet. Full text in Research Archive
• Din, Muhammad Naseer ud; Ytterdal, Trond & Aunet, Snorre (2024). Ultra low voltage arithmetics- Schmitt trigger based vs Static CMOS. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  The demand for low-power and energy-efficient digital systems has increased in recent years for various applications. Ultra-low-voltage circuits have become popular in low-power applic- ations but face performance degradation. This report analyzes the operation of static CMOS and Schmitt trigger (ST) CMOS-based full adders, full adders connected as ring oscillators, and ripple carry adders in the subthreshold region. Full adder implementation using Schmitt trigger CMOS XOR can save 50% average power as compared to full adder implementation using static CMOS XOR, while full adder implementation using Schmitt trigger CMOS NAND gate can save 31% average power as compared to full adder implementation using static CMOS NAND gate at TT corner, 0.18V and 27°C. Additionally, the report provides a complete DC voltage transfer analysis with analytical expressions for the N MH and N ML. A comparison between the ST CMOS and static CMOS adders reveals the relative benefits, such as a high and stable noise margin, with the temperature rise, while presenting drawbacks, such as larger size requirements of each in ULV applications. Propagation delay is higher for Schmitt trigger CMOS full adders than static CMOS full adders for all process corners at 0.18V and 27°C. Furthermore, the study includes a thorough investigation of measured propagation delay, av- erage power, power delay product, and energy-delay product of the circuit when full adders are connected in the ring configurations and also in the ripple carry adders configuration. In-ring oscillators at TT corner, 0.18V and 27°C, ST CMOS NAND save 16% average power than static CMOS NAND, ST CMOS XOR save 66% average power than static CMOS XOR configuration. In the RCAs at TT corner, 0.18V and 27°C, ST CMOS NAND saves 43% av- erage power than static CMOS NAND, ST CMOS XOR saves 53% average power than static CMOS XOR configuration. Keywords: Schmitt trigger, Static, Subthreshold, CMOS, N MH , N ML, delay, Power, PDP, EDP, Ring, RCA.

• Zareian, Fatemeh; Ytterdal, Trond & Aunet, Snorre (2024). Design of Schmitt Trigger Based SRAM Bitcell for Sub-100mV Operation in 90nm Technology. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Innenfor Internet of Things (IoT)-sensor noder er oppnåelse av ultralavt strømforbruk avgjørende for å muliggjøre kontinuerlig drift gjennom energihøsting. Denne oppgaven undersøker design og ytelse av CMOS Schmitt Trigger (ST) invertere, NAND2 porter og SRAM bitceller under lave forsyningsspenningsforhold, spesifikt under 100mV, for å adressere strømbegrensningene i IoT-applikasjoner. Studien begynner med teoretiske innsikter som fremhever fordelene ved ST-topologi som opererer i subterskelområdet, med vekt på høyere på-til-av-strømforhold og forbedrede støymarginer. Metodedelen oversetter teori til praktiske designbetraktninger, med vekt på viktigheten av å balansere styrken til pull-up og pull-down-nettverkene, velge HVT NMOS-typen og velge riktige transistorstørrelsesforhold for portene og SRAM bitcell-topologien. Resultater fra Cadence Virtuoso GPDK 90nm-simuleringer viser den robuste ytelsen til de designede kretsene, som konsekvent møter det målrettede utbyttet for forsyningsspenninger som overstiger 60mV for portene og 70mV for SRAM bitcellene. Videre utforsker studien støymarginene og stabiliteten til portene og SRAM bitcellene over ulike forsyningsspenninger, temperaturer, transistoravvik og prosesshjørner. Det observeres at temperaturvariasjoner generelt reduserer støymarginene, og det er en betydelig reduksjon i støymarginen i SF-hjørnet. Når det gjelder SRAM bitceller, sammenligner forskningen 14-transistor og 12-transistor konfigurasjoner, og viser at 12-transistor designen kan oppnå sammenlignbare statiske støymarginer (SNM) for skrive-, lese- og holdetilstander til tross for reduksjonen i antall transistorer. Denne funn antyder at 12-transistor bitcellen er et levedyktig alternativ for lavspenning, lavstrømsapplikasjoner. Samlet sett bidrar denne oppgaven til forståelsen av lavspennings CMOS-kretsoppførsel, og gir praktiske designretningslinjer for å forbedre stabilitet og robusthet gjennom økte støymarginer. 12-transistor SRAM bitcelle-designet understreker potensialet for å redusere transistorantallet uten å ofre ytelsen, og tilbyr dermed en vei til mer effektive IoT-enheter. Dette arbeidet legger et grunnlag for fremtidig forskning rettet mot ytterligere optimalisering av lavstrøms CMOS-design og integrering av disse i komplekse systemer for energieffektive IoT-applikasjoner.

• Bertelsen, Patric Andre; Marchuk, Vitaly; Vestli, Snorre; Waagen, Johannes & Aunet, Snorre (2024). Optimizing Routing Architectures for Small-Scale Heterogeneous Systems. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  This work aimed to find a routing architecture for a small FPGA integrated alongside an MCU, based on specifications given by Microchip Technology. The design needed to fit MUX-based technologies, with no tri-state buffers. It needed to be scalable to some degree, could route most designs (within reason), and needed to be area efficient (regarding the number of MUX2 gates). This work looked at 2 different routing architectures, namely the route-through and bus architecture. In order to evaluate these architectures, then 5 different Verilog test designs were used (i.e., AND4, ADD2, SR4, SR8 and SR15), with the addition of a cost estimation metric, as well as an estimated route-through and logic utilization percentage of the architecture. The results showed that the route-through architecture could route all test designs with a grid size of (4, 8), with 7 INTRA wires and 4 INTER wires per tile. The architecture had around 6x the cost of previous architecture used by Microchip. The bus architecture failed to route any design, with a cost around 4x times that of the previous architecture used by Microchip. Most of the tests performed on the route-through architecture had a higher percentage of logic utilization for a grid size of (4, 8), and a higher percentage of route-through utilization for a grid size of (8, 4). Some tests did not work for a grid size of (8, 4) due to a lack of sufficient amount of inputs. This work also looked at the relationship between the INTRA and INTER parameters for the route-through architecture. The results showed a 37% variation in the total amount of placed blocks for the various tests, primarily for a grid size of (4, 8). The question of whether block placements or routing resources run out first on the device was also discussed, where ideally, block placement should be the factor that runs out first. Several observations were made that warrant further study. Occasional routing loop errors could be mitigated by the use of automated test scripts. Further development might also benefit from using a different PnR tool, with potentially a working GUI. A new metric for blocks that have both route-through and logic functionality could help gain more insight into routing congestion issues. Additional observations were made in terms of the PWR block and device clock.

• Gundersen, Julian Vold; Kjæxli, Even Aleksander Sneve; Ytterdal, Trond & Aunet, Snorre (2024). Design & Verification of a Sub-100mV Standard Cell Library in 130nm SoI CMOS. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Det stadig økende behovet for digitale kretser med lavt effektforbruk utfordrer designere til å utvikle nye teknikker for å tilfredsstille strengere krav. Subterskel operasjon viser lovende resultater for applikasjoner der drift med lave spenninger og lavt effektforbruk er de primære begrensingene. Systemer drevet av energihøstere og lav-effekts IoT noder kan spesielt dra nytte av subterskel operasjon. Standardcellebiblioteket utviklet i dette prosjektet bruker Schmitt–Trigger topologier realisert i 130nm SoI teknologi for å oppnå robust operasjon ved en nominell forsyningsspenning på 85mV. Realistiske, ikke–ideelle forhold tas i betraktning ved å kjøre Monte Carlo simuleringer med transistor mismatch og prosessvariasjoner. De enkleste logiske portene oppnådde yield over 99.9% ved nominell spenning, og ble brukt i syntese av større systemer. Totalt fem full–addere og fem minority–3 porter ble evaluert og vurdert for cellebiblioteket. Blant de fem minority–3 portene, er en ny struktur foreslått ved å bruke Schmitt–Trigger prinsipper for å minimere lekkasje. For større kretser ble én seriell og to parallelle addere evaluert basert på arealkrav, strømforbruk og energieffektivitet. Analyser av disse viste at seriell addisjon kan være mer energieffektivt enn parallell, med samme forsinkelse, hvis en økning i forsyningsspenning med omtrent 50mV kan tolereres.

• Hollingen, Eirik; Marchuk, Vitaly & Aunet, Snorre (2024). "Optimal routing for a scaleable configurable logic in a heterogeneous system" done in cooperation with Microchip. NTNU. Full text in Research Archive
• Øfsti, Gjermund Sollien; Hasanbegovic, Amir & Aunet, Snorre (2024). NIRCA MkII DevKit Firmware Development. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  NIRCA MkII Development Board(NM2DB) er en PCB med NIRCA MkII(NM2), en ASIC brukt til kontroll og utlesning av infrarøde sensorer. PCBen har også en Trenz FPGA "system-på-modul" brukt til kontroll av ASICen, LDOer og for kommunikasjon mellom PCBen og en Frame Grabber fra Matrox koblet til med en Camera Link kabel. Masteroppgaven involverer utvilking av firmware for Trenz modulen med VHDL og software for å kommunisere med NM2DB fra PC. Firmwaren har UART kommunikasjon mellom frame grabber og PCBen i tillegg til SPI kommunikasjon mellom til og fra NM2. Resultatene i oppgaven viser at firmwaren utklasser den tidligere implementasjonen brukt på samme PCB. Dette er gjort ved å bytte bort fra Ethernet TCP kommunikasjon til å bruke mer optimisert python-kode til å skrive og lese data til NM2DB. Den endelige implementasjonen bruker en UART port som kjører på 460 800 baud og en SPI med frekvens 10MHz. En full lese og skriveoperasjon til ca. 4600 registre på NM2 tok 2 sekunder mens gammel TCP software og hardware brukte omtrent 45 sekunder.

• Mahabadi, Zahra Jenab & Aunet, Snorre (2023). High Level Power Modelling for IoT. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Målet for denne masteroppgaven er å modellere effektforbruket til et system på en chip på elektronisk systemnivå ved å bruke effekt- og ytelsesmodelleringsverktøyet Fused. Motivasjonen bak prosjektet er å få et estimat på effektforbruket til et system tidlig i designløpet. Effektmodelleringen ble utført ved å instrumentere komponenter i systemet som fra tidligere simuleringer er antatt å ha høyt effektforbruk, og som det fins tilgjengelige data om effektforbruk om fra datablad eller tidligere simuleringer. De instrumenterte komponentene er to prosessorer, referert til som core 1 og core 2, et hurtigminne, referert til som cache, tre minner referert til som memory 1, memory 2 og memory 3. Fire eksperimenter ble utført. I det første ble CoreMark kjørt på core 1 fra memory 3 og med cache aktivert, og den virtuelle prototypen var instrumentert med verdier for energi- og strømforbruk tatt fra komponentdatablader, samt enkelte verdier fra tidligere effektestimeringer. I det andre ble CoreMark kjørt på core 2 fra memory 1 og 2 med cache deaktivert, her og med verdier fra komponentdatablader og tidligere effektestimater. Det tredje er en gjentakelse av det første, men med energi- og strømforbruksverdier tatt fra et PrimePower- estimat av RTL- modellen. Det fjerde er en gjentakelse av det andre, her og med instrumenteringsverdier tatt fra PrimePower. Eksperiment 1 gir et gjennomsnittlig root- mean- square- avvik (RMSE) på 0.012 W / sample. Eksperiment 2 hadde et gjennomsnittlig RMSE på 0.54970.012 W / sample. Eksperiment 3 hadde et gjennomsnittlig RMSE på 0.01330.012 W / sample. Alle resultater er normaliserte grunnet konfidensialitet. Eksperiment 4 gir et gjennomsnittlig RMSE på 0.2502. Kurvene av estimert effekt per tid på elektronisk systemnivå og registeroverføringsnivå samsvarer delvis i form. Som konklusjon virker denne metoden for effektmodellering lovende, men den forutsetter at fornuftige verdier for energi og strøm til hendelser og statuser blir brukt. Det er også viktig å ha i minne at det kan være mindre forskjeller i hvordan den virtuelle prototypen og en registeroverføringsnivåmodell eller en fysisk chip fungerer, og at dette kan påvirke effektforburkskurvene noe. Imidlertid vil metoden være nyttig for å gi et bredt estimat av effektforbruket til systemet under en gitt arbeidslast.

• Overholt, Ingvild Una Sundsby; Villafuerte, David Luis Lopez Tello & Aunet, Snorre (2023). High Level Power Modelling for IoT. Norges Teknisk Naturvitenskapelige Universitet. Full text in Research Archive
• Skirbekk, Asta; Ytterdal, Trond & Aunet, Snorre (2023). Design of SRAM for Sub-100mV Operation Using 22 nm FD-SOI. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Energy harvesting is a promising solution for Internet of Things (IoT) devices, as this removes the need for frequent changes of batteries. Many energy harvesting solutions struggle to supply a high voltage, and this provides a problem for on-chip memory which is often volatile and therefore requires a reliable power supply at all times. On-chip memory must therefore be designed to work at ultra low supply voltages. The objective of this master's thesis has been to use a 22 nm FD-SOI (Fully Depleted Silicon On Insulator) transistor technology to create a custom Static Random Access Memory (SRAM) for sub-100mV operation and to study how the minimum supply voltage is affected by process variation and transistor mismatch. To achieve this one must also carefully design and study the SRAM's subcircuits, and this has therefore been a major part of this project. As minimising the supply voltage has been the aim, this has been done even when it is at the cost of higher power consumption and/or an increased chip area compared to SRAM circuits operating at higher supply voltages. The SRAM was designed to operate at temperatures in the range 0°C to 50°C, as this would allow it to be used in most indoor applications as well as in medical applications. Physical layouts were created for a 4B SRAM, 16B SRAM, and a 64B SRAM, as well as for all the SRAM's subcircuits, to get more reliable and accurate simulation results. The three SRAM layouts were found to operate at a minimum supply voltage of 85 mV when process and temperature variations were considered. The SF corner had the worst post layout performance for all circuits, and it was concluded that better balancing of the PMOS and NMOS transistors would improve the performance in this corner considerably. This improvement can be done by changing the transistor sizing strategy slightly as well as switching from merged to non-merged transistors in the layout. Monte Carlo simulations of transistor mismatch were run on the 4B SRAM and the 16B SRAM, and good post layout yields were achieved for a supply voltage of 80 mV with yield_{4BSRAM,80mV}=97% and yield_{16BSRAM,80mV}=97.6%. The performance of the SRAM's subcircuits indicate that the yield will remain high for larger SRAM circuits as well.

• Akre, Erlend; Aunet, Snorre; Wisland, Dag Trygve Eckhoff & Kjelgård, Kristian Gjertsen (2023). Ultra Low Power Digital Oscillator with Dynamic Leakage Suppression and compensation In 65nm BULK CMOS and 22nm FDSOI. Universitetet i Oslo, Fysisk Institutt. Full text in Research Archive
• Abdoliniafard, Erfan; Shakouri, Shima; Qadir, Omer; Dieset, Herman Kristian & Aunet, Snorre (2023). Design and Analysis of a Voltage Controller for Memristor-based In-memory Computation. Norges Teknisk Naturvitenskapelige Universitet. Full text in Research Archive
• Slagstad, Karsten Sedal; Marchuk, Vitaly & Aunet, Snorre (2023). Optimal Implementation of Configurable Logic Framework in AVR Microcontrollers. Norges Teknisk Naturvitenskapelige Universitet. Full text in Research Archive
• Aguiar, Daniel Eduardo Guarecuco; Ness, Torbjørn Viem & Aunet, Snorre (2023). Multi-dimensional exploration of the Minimum Energy Point for RISC-V subsystem in 22 nm FDSOI. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Battery operated devices are highly constraint in energy budget, there is a need for energy-efficient designs. Designing circuits to operate in the Minimum Energy Point (MEP) yields great energy savings, by at least 20%, by reducing supply voltage and operating frequency. The MEP is in the near or sub-threshold region, such that the circuit becomes very sensitive to PVT variations. This thesis proposes a methodology to study and locate the MEP and its relationship with supply voltage, threshold voltage, channel length, body biasing, temperature and process variations, for a RISC-V Ibex CPU synthesized with standard cell libraries characterized for higher voltages with a commercially available 22 nm FDSOI technology. A critical path replica is converted into a ring oscillator for running SPICE simulations. The simulations are used to estimate the MEP of the CPU. Results show that HVT and UHVT libraries are unfit for operating at the MEP due to a huge gap between slow and fast corners. It is shown that SLVT provides the best timing closure. The selection of threshold voltages becomes the most important parameter, adjustments can be made later by selecting a proper channel length and body-biasing voltages.

• Laurentui, Erhan & Aunet, Snorre (2023). Air Flow Sensor - Wireless and Battery Powered. Norges Teknisk Naturvitenskapelige Universitet. Full text in Research Archive
• Moen, Ole-Tobias; Hasanbegovic, Amir & Aunet, Snorre (2023). Camera Link transmitter for high bandwidth ADC data readout. Norges Teknisk Naturvitenskapelige Universitet. Full text in Research Archive
• Chen, Yini; Aunet, Snorre & Wisland, Dag Trygve Eckhoff (2023). Frequency Σ ∆ Modulator with ultra-low power supplies towards sub-100 mV. Universitetet i Oslo. Full text in Research Archive Show summary

  This master thesis centers on the exploration of a frequency delta-sigma modulator (FDSM) with ultra-low power supply down to 80 mV for the analog circuitry. The FDSM is configured with ring voltage controlled oscillator (RVCO) serving as the integrator, and two D-flip flops with one as a counter and the other one as a register, finally a differentiator to separate the quantization error from the signal. All components are operated in the subthreshold region as they are supplied with voltages of 80 and 100 mV. Schmitt trigger based logic gates are employed in the entire circuit as the topology is proved to be operational and robust with ultra-low power supply in several sources. This design offers an unconventional solution to ultra-low power supply limitations, by employing an undersampling of the RVCO under an oversampling method of the overall system. Various simulation results are presented in this thesis, as well as the design choices and analysis of the output signal in both time and frequency domain. This design has the potential for applications such as biomedical devices for monitoring heartbeats and blood pressure, as well as sensor interfaces for self-powered IoT products.

• Nägle, Louisa Charlotte; Klarhorst, Christian; Hagemeyer, Jens; Rückert, Ulrich & Aunet, Snorre (2023). Design of Basic Digital Cells for Deep Subthreshold Regime using Schmitt Trigger Logic. Universität Bielefeld. Full text in Research Archive
• Amble, Magnus; Kjelgård, Kristian Gjertsen; Wisland, Dag Trygve Eckhoff & Aunet, Snorre (2023). Cryptographic hardware resistant to Leakage-Based Differential Power Analysis Attacks. Universitetet i Oslo. Full text in Research Archive
• Bogevik, Olav; Qadir, Omer & Aunet, Snorre (2022). Evaluate potential of approximate multipliers for energy efficient inference in DNNs. Norges Teknisk Naturvitenskapelige Universitet. Full text in Research Archive
• Sæther, Harald; Ytterdal, Trond & Aunet, Snorre (2022). A Sub-100mV Supply Voltage Standard-Cell Based Memory in 22nm FD-SOI. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  The desire for reduction in power consumption has motivated the design of integrated circuits operating in the sub-threshold domain. Circuits operating at sub-threshold supply voltages need robust architectures and techniques, that can withstand effects that are pronounced in the sub-threshold domain. Effects such as an increased sensitivity towards process variation and a diminished on-to-off current ratio can negatively affect the circuit functionality. Many applications such as energy harvesting in mm-scale nodes and biomedical devices, desire reliable and efficient integrated circuits that have as low of a supply voltage as possible. Currently, charge pumps/voltage converters, that have bad efficiency, need to be used to convert the output voltage of an energy harvester into a higher voltage, which the rest of the circuit runs on. This costly conversion can be reduced or avoided if the rest of the circuit runs at as low of a supply voltage as possible. Memory is often used in complex digital circuits like mm-scale nodes and biomedical implants, occupying a vast amount of circuit area, and is thus a component where huge power savings can be gained if memory is designed at as low of a supply voltage as possible. In this thesis, such a memory is designed for operation at sub-100mV supply voltage. Where robust techniques are applied at the transistor to architectural abstraction level of the memory. Several classic static logic gates are benchmarked in terms of power, performance, layout area, against so called Schmitt Trigger-structures that have been proven to operate at very low supply voltages. From standard cells(NAND, NOR and NOT -logic gates) a simple standard cell-based memory(SCM) is constructed which includes structures such as multiplexers, decoders, pre-decoders, clock gates and data-flip-flops(DFF). The constructed memory is then simulated and modelled to verify functional chip yield for a supply voltage of 87 mV. The complete SCM which is 1024-bits in size, with 128 different addresses, storing 8-bits of data at each address, shows good functional chip yield, with the lower bound of yield above 90% with a maximum redundancy of 4. Operating frequency is 150Hz, with an average power consumption of 6.991nW. The SCMs total layout area is 338741.1µm2.

• Saure, Runar Andre; Bakke, Glenn Ruben Årthun & Aunet, Snorre (2022). Using a processor for memory-efficient GUI display driving. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Mikrokontrollere blir stadig sterkere, og mer avanserte teknologier dukker stadig opp, spesielt innen utivklingen av innvevde systemer. Det virker logisk å bruke disse sterkere enhetene i mer komplekse innvevde systemer som bruker menneske-maskin grensesnitt, men det å kutte kostnader er også alltids en prioritet. Ved å benytte teknikker for å begrense RAM- og CPU-forbruket gjennom en linje-definert beskrivelse av det grafiske grensesnittet, virker det mulig å optimalisere lav-kostnads mikrokontrollere til å drive grafikk bedre. Modellen som ble implementert i dette prosjekte var av en høynivås-art, og ble testet opp i mot en referansemodell basert på mer vanlige rendering-teknikker. Implementasjonen ga en enorm forbedring i RAM-forbruk, med det minste forskjellsgapet på 26 785% i forskjell til fordel for linje-beskrivelsen, dersom man ikke tar hensyn til kompresjon. Kjøretiden var derimot værre, og den slet med å henge med referansemodellen i timingen per linje. Gitt grunnlaget oppgaven har undersøkt, er det mulig å bygge videre på og optimalisere systemet videre, for eksempel gjennom å implementere en lavnivå-modell for å bedre treffe kjøretiden til referansemodellen.

• Zadeh, Somayeh Hossein; Ytterdal, Trond & Aunet, Snorre (2022). Energy Efficient Subthreshold Digital Building Blocks. Norges teknisk-naturvitenskapelige universitet. ISSN 9788232663163. Full text in Research Archive Show summary

  Many IoT applications such as implantable biomedical devices, sensor nodes in the internet of things operate in the kHz range, and power consumption is the primary concern in such applications. However, the required voltage of the most implantable electronic devices is 2-3 V [47]. The output properties of the most recent in vivo energy harvesters (IVEHs) is 150 mV and below [47, 61] which could suit the low voltages for the subthreshold circuits, while saving energy by not having to use as energy costly DC-DC conversion as one would for higher supply voltages. Therefore, subthreshold circuits operating at the supply voltages lower than the absolute value of the threshold voltage of the transistors might be the best option for such applications. The power consumption is reduced as the circuit supply voltage is lowered down towards and below the threshold voltage of the transistors, but it will increase the propagation delays. It may not be a concern for low to medium performance. Voltage scaling in integrated circuits brings challenges for a designer that has to be considered during the design phase. The impact of the process, voltage, and temperature variations increases by voltage scaling and affects the functionality of the circuits. This thesis focuses on designing and exploring energy efficient computing and memory circuits at ultra low voltage subthreshold regime at the different abstraction levels. Techniques such as body biasing (reverse body bias), transistor stacking, device sizing, multi-threshold voltage devices at the gate level have been explored to reduce the power consumption especially static power, taking into account the reliability issue and process, voltage and temperate variations. At the circuit level, different topologies of the full adders based on the standard CMOS designed for subthreshold supply voltages have been compared considering the functionality and reliability issues. In addition, an optimal back gate bias has been proposed in a commercially available 22 nm FDSOI (Fully Depleted Silicon On Insulator) technology that minimizes the energy per operation consumption of subthreshold digital CMOS circuits and improves the reliability. The adder as a case study under optimal body bias consumes 4.6 percent less energy than zero body bias at Vdd=150 mV and a frequency of 1 kHz. At the architectural level, two different types of adders including Kogge Stone adder (KSA), the fastest adder, and the Ripple Carry adder (RCA), the simplest adder have been designed and fabricated for supply voltages as low as Vdd = 140 mV. The adders have been synthesized at the gate level using full custom standard cell library designed for ultra low voltage subthreshold regime. The gap between simulation and measurement results is filled with successful implementation and comparison of the ultra low subthreshold adders at such a low voltage 140 mV. To the best of the authors knowledge this is the first measurement comparison between two different adder architectures for ultra low supply voltages as low as 140 mV. Simulated results in [7] indicated that the RCA is 1.36X energy efficient compared to the KSA at the same speed. Measured results presented here, show that the RCA is 4.15X to 1.92X energy efficient compared to the KSA at supply voltages between 250 to 500 mV. In addition, the RCA designed in this study outperforms the reported works in terms of a defined FoM which is (Tech)=(Vmin:Energymin). Digital circuits designed for applications like sensor networks, implantable biomedical devices and environmental monitoring need to work at different conditions. For example, the temperature range that circuit should work. In this thesis, we have studied the performance of the circuits at different temperatures, supply voltage and in the presence of mismatch and process variations. The multiple threshold voltage technique has been used to design a 7T loadless SRAM cell for subthreshold regime, and demonstrate the different trade offs for single, regular and flip well types SRAM memories. Among all devices used (HVT, RVT, LVT and, SLVT) available in a commercially available 22 nm FDSOI technology, the best combination for minimizing energy per access is HVT devices as the driver transistors and RVT for the rest of the transistors. The single well SRAM has the lowest leakage per bit cell over its regular and flip well counterparts. The regular well type has lower static noise margin (SNM) variability. An 8-bit RCA has been designed by using multiple threshold voltage technique in 22 nm FDSOI technology. The simulation results based on the extracted netlist from layout show that the energy per one bit addition is lowest in our adder compared to the proposed adders in FDSOI technology. The energy per one bit addition for the proposed adder at Vdd = 300 mV is 0.23 fJ. We have also used the dynamic body bias technique for the adder to balance the PUN/PDN (Pull up/Pull down networks). The results show that the adder with dynamic body bias is robust and functional at the supply voltage 60 mV lower that that of the adder with conventional body bias. Additionally, a new standard cell memory based on the NAND race free D-latch has been synthesized and explored. The simulation results show that using robust NAND race free D-latch leads to lower minimum operating supply voltage, and hence, lower power and energy for standard cell memory. This dissertation analyzes subthreshold digital circuits using 22 nm siliconon-insulator process and 130 nm bulk CMOS technology. We also fabricated and tested the digital circuits in 130 nm technology and the measurement results are compatible with the simulation results.

• Sarker, Anjan & Aunet, Snorre (2021). Analysis, comparison and implementation of open-source Floating Point Units for energy harvesting applications. Norges Teknisk Naturvitenskapelige Universitet. Full text in Research Archive
• Rud, Markus; Moldsvor, Øystein & Aunet, Snorre (2021). Power and energy consumption in hardware implemented SPI master devices. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  This thesis presents an analysis of two different VHDL designs of the SPI master device implemented onto a model of a FPGA. The analysis is focused at power and energy consumption in the devices compared with provided functionality. The two devices differ in their design strategy where one is created as a simple design where only the required logic to conduct a SPI transmission are implemented. The second one is a more complex design where it is possible to adjust transmission parameters such as setup and hold time after implementation and a more complex interface to the controlling logic which controls the SPI masters. The complex implementation also implement two FIFO registers to store multiple messages during transmission and reception. The conducted analysis is based upon different tests in order to give an understanding of which elements of a SPI master who impact the energy consumption in the device. These tests look into the impact of operating frequency, communication frequency, operation mode and alternation to the utilized logic. The designs are implemented onto a model of a FPGA using the development tool Vivado. The two designs are also power optimized using the build in power optimizer in Vivado. The results from the analysis show that when implementing a SPI master, it is necessary with a trade of between functionality and energy consumption. The different implementations are analysed over a frequency span of 1 MHz to 15 MHz where it is seen that the complex master requires 27.2% more energy than the simple master on average. It is therefore seen that a higher complexity in the design requires more energy. The complex master utilize more than twice as much logic, but not twice as much energy, so the energy cost of added functionality is therefore heavily dependent on the switching activity in the added logic. The results also show that it is preferable to operate the tested SPI masters at the highest frequency possible within the tested frequencies since this gives the lowest energy consumption. This result is to some extend limited by the implementation method as the implementation of the SPI master onto a FPGA removes some potential benefits of operating the design at a low frequency such as smaller transistor sizes and lower operating voltage. It is also seen that the two SPI designs react relatively similar to adjustments to transmission parameters such as communication frequency and operating mode since their percentage energy difference with adjustments are approximately similar for both designs. The analysis consist of some limitations. The SPI masters are analysed as standalone devices not connected to any controlling device which limits the energy analysis due to missing timing delays. The SPI masters are also relatively small designs so when implemented on a large FPGA compared to the designs, a large static power overhead is added which can hide the actual static power consumption for the designs themselves.

• Skavnes, Solveig; Moldsvor, Øystein; Hagen, Anders Ivar & Aunet, Snorre (2021). Design and Implementation of a Magnetic Energy Harvesting System for Low Primary Current Applications. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Energihausting er å utnytte små mengder omkringliggjande energi for å drive eit lavenergisystem, slik som for eksempel ei sensornode. Dette kan gjerast frå magnetfelta som kjem frå ein vekselstraum, Ip, som går gjennom ei leidning. Målet med masteroppgåva er å utvikle eit system som klarer å levere 3,3 V ut for å lade eit batteri, mens Ip er under 1 A. Systemet burde fungere for Ip-ar under 1 A, sidan dette mogleggjer at systemet kan lade eit batteri mykje av tida, sjølv om det ikkje går høge vekselstraumar gjennom leidninga. Eit magnetisk energihaustingssystem kan bestå av ein straumtransformator (engelsk: Current Transformer) eller CT, ein likerettar og ein DC/DC-omformar. Eit slikt system er designa, simulert ved bruk av SPICE og implementert ved å bruke komponentar på eit breadboard. Dei ulike undersystema er testa individuelt og saman. Fem ulike CTar er testa. Tre ulike likerettarar er designa og testa, og to ulike DC/DC-omformarar er testa. Dette blir totalt 30 undersystemkonfigurasjonar, kor tre av dei oppfyller kravet om å fungere ved Ip < 1 A. Den kombinasjonen av undersystem som klarar å levere 3,3 V ut med den lavaste Ip inn er kombinasjonen av ein CT med 1:2000 vindingsforhold, ein likerettar basert på schottkydioder og ein DC/DC-omformar som har ein høg inngangsmotstand. Dette systemet leverer 3,3 V ut ved Ip = 0,5 A. Dei tre undersystemkonfigurasjonane som oppfyller kravet er alle saman testa og verifisert at dei fungerer opp til Ip = 16 A. Eit kommersielt energihaustingssystem med kombinert likerettar og DC/DC-omformar er testa som ei samanlikning, med dei same fem CTane testa tidlegare. Dette systemet er LTC3331 og saman med ein CT med 1:2000 viklingsforhold treng dette systemet Ip = 5 A for å levere 3,3 V ut, noko som er signifikant dårlegare enn det beste systemet som er designa og testa i denne masteroppgåva.

• Rotevatn, Synnøve Andersen; Barzic, Ronan & Aunet, Snorre (2021). Automated Desynchronization Using Pyverilog. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive
• Auseth, Øivind Nielsen,; Aunet, Snorre & Ness, Torbjørn Viem (2021). Modelling of Cache/Interconnect Performance in an Embedded System. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Cache og bus topologi i et innvevd system har en stor innflytelse på systemets ytelse og energi effektivitet. Å produsere en ny chip for testing er dyrt, og dette har gjort simulering av arkitektur forandrnger til en vanlig praksis i industrien. Moderne RTL simuleringer kan gi veldig nøyaktige estimater av ytelsen til integrerte kretser. Å modellere en arkitektur for en slik simulering er en lang og arbeidskrevende prosess, og å modifisere modellen er ofte tidkrevende. Det er et behov for en rask og enkel måte å eksperimentere med forskjellige bus topologier, som fortsatt klarer å gi et godt estimat på hvordan forandringer vil påvirke ytelse. Denne avhandlingen presenterer en modell som er lett å bruke, og som gjør det mulig å fullstendig forandre en arkitektur ved å bare modifisere et par verdier i en tekst fil. Modellen bruker en node-tre representasjon av bus hierarkiet, og abstraherer vekk deler av arkitekturen som er vanskelig å modellere, slik som timing jitter når man krysser klokkedomener og bus contention. Hver node representerer en komponent i interconnect topologien og sier eksplisitt hvor mye latency den legger til en minneaksess. Dette gjøre det mulig å skrive en veldig forenklet arkitektur beskrivelse, som bare fokuserer på de aspektene av bus topologien som bidrar mye til minneaksess ytelsen. Bus topologien som er simulert for testing i denne avhandlingen er den sentrale Cortex-M33 prosessoren på Nordic Semiconductor sin nRF5340 SoC. Simuleringsresultatene ble sammenlignet med tester som kjørte på et nRF5340 development kit. Når Coremark ble simulert med cache aktivert, rapporterte modellen en kjøretid som var 18.70\% lengre enn kjøretiden på hardware. Når Coremark ble simulert med cache deaktivert, rapporterte modellen en kjøretid som var 4.36\% lengre enn kjøretiden på hardware. Når sekvensielle aksesser til matriser ble simulert, rapporterte modellen 68\% flere instruction cache hits og 18\% færre latency sykluser enn hardware for de minste matrisene, og 50\% flere instruction cache hits og 5\% færre latency sykluser enn hardware for de største matrisene. Modellen viste høy fidelity, men de simulerte resultatene var forskyvet sammenlignet med resultatene fra hardware. Den er nyttig for å spå om en forandring vil øke eller senke instruction cache ytelsen og den totale mengden latency sykluser. Det var problemer utenfor omfanget av denne avhandlingen som var betydelige feilkilder i resultatene. I tidlig testing av hvordan modellen ville yte hvis problemene ble løst, så rapporterte den cache hit og cache miss resultater som var innen 0.2\% av resultatene som ble sett på hardware, og cache latency resultater som var 7.3\% høyere enn resultatene som ble sett på hardware. Dette viser at modellen har potensialet til å gi veldig nøyaktige resultater og være et nyttig verktøy for tidlig utforskning av hvordan modifikasjoner av cache og bus topologi vil påvirke ytelse.

• Steinsland, Christian Rosioara; Aunet, Snorre & Ytterdal, Trond (2021). Design and Implementation of a Digital Standard Cell Library for 28 nm Technology. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  A digital standard cell library has been designed and implemented for a 28 nm technology. The library has been designed and optimized for a supply voltage of 300 mV, to be compatible with a standard design flow. Each cell has been characterized with extracted parasitic components. Combinatorial logic gates, including compound logic gates, and sequential cells were implemented with SLVT (Super Low VT) transistors. The library has been used to synthesize a functional RISC-V architecture (PicoRV32). The motivation was to verify the functionality of the standard cell library and obtain quantitative results of the performance of the library. The minimum energy point (at room temperature in the TT-corner) for the CPU was found to be with a supply voltage of 500 mV and a frequency of 20 MHz. By increasing the supply voltage to 600 mV, the CPU supports a 50 MHz clock. The highest simulated frequency was 250 MHz at 1 V

• Låte, Even; Ytterdal, Trond & Aunet, Snorre (2021). Low Voltage Logic and Memories on Silicon. Norges teknisk-naturvitenskapelige universitet. ISSN 9788232669714. Full text in Research Archive Show summary

  Data centers, sensor nodes in the internet of things, and handheld devices are all systems that require energy efficiency and low power operation to reduce electricity cost, fit within power budgets of energy harvesters, avoid overheating or increase battery lifetime. These requirements can be achieved by lowering the supply voltage of their integrated circuits. The power consumption is reduced as the circuit supply voltage is lowered down towards and below the threshold voltage of the transistors; this comes at the cost of increased propagation delays. There exists an application-dependent sweet-spot for the supply voltage referred to as the minimum energy point, where the energy per operation of the circuit is at its lowest. Voltage scaling in integrated circuits requires considerations during the design phase. Even though down-scaling the supply voltage of integrated circuits is a popular and effective means of achieving these goals, the relative impact that process, voltage, and temperature variations have on the functionality of the circuits also tend to increase with decreasing supply voltage. For memory subsystems within low power and energy-efficient circuits, variations in strength ratios between transistors can lead to an inability to write, inability to read, or inability to hold logic values. In this work, promising synchronous edge-triggered memory elements have been identified for low voltage operation. A comparative study of 9 data flip-flop circuit architectures at a target supply voltage of 200 mV has been performed. In the study all nine memory cells were sized and laid out using the same approach, setup time, hold time, minimum functional supply voltage, propagation delay, functionality in Monte Carlo simulations, power consumption and energy per cycle have been simulated for each data flip-flop on netlists extracted from the layout. The study revealed that the two most promising memory elements were the Pass Gate and the PowerPC flip-flops. The first had the lowest energy consumption per cycle for operating frequencies below 500 kHz, and for supply voltages below 400 mV, the lowest transistor count and the smallest layout footprint, it was also functional at the lowest supply voltage of 65 mV. The second, the PowerPC flip-flop, had the best power delay product, 26% of that of the worst flip-flop. Compact near-threshold static random access memory cells have also been investigated. Many Low voltage SRAM cells have been reported in the literature. However, most of them deploy multiple extra transistors as write- and read- assists to the conventional 6 transistor SRAM cell. We bring the loadless 4 transistor cell down to the near-threshold voltage domain by adding a 2 transistor read buffer. The loadless nature of the 4 transistor core acts as a write assist while the 2 transistor read buffer acts as a read assist, ensuring read-ability and write-ability at a supply voltage of 350 mV in a 28 nm fully depleted silicon on insulator technology for a 6 T cell. High sigma simulation results on a 128 kb memory macro of the cell show that it performs on par with state of the art low voltage memory. Three variants of the macro were explored where the peripheral logic consisted of low threshold-voltage, high threshold-voltage devices, and high threshold voltage devices with up-scaled lengths. For the three variants at a supply voltage of 350 mV, the retention power consumption of the 128 kb system was found to range from 1.31 μW to 71.09 μW, the maximum operational frequency was found to lie within 1.87 MHz and 14.97 MHz while the read energy varied from 13.08 to 75.21 fJ/operation/bit. The minimum retention voltage of the loadless SRAM cell was found to be 230 mV in Monte Carlo simulations. A study has been performed where we balance pull-up and pull-down networks in ultra-low-voltage logic gates to maximize noise margins and create robust lowpower minority-3 and Boolean logic gates. To balance the drive strength of the complementary networks in the gates, design-phase gate-length biasing and runtime back-gate biasing was applied. These gates have been combined into ultralow voltage 16- and 32- bit adders, and measurements were made on a physical prototype. The improvement in energy per 1-bit addition for the 32-bit adder was 37% at a supply voltage of 300 mV compared to the best reported adder in the same technology. For the 16 bit adder, the improvement was 25% at a supply voltage of 250 mV. In addition, the 32-bit adder was shown to be functional down to 125 mV for all ten chip-samples and down to 80 mV by tuning the drive strength of the pull-up networks, with back-gate biasing. To interface ultra-low-voltage circuit blocks, subthreshold to superthreshold level shifters have been examined. By applying the principle of write assist circuitry in low voltage memory cells to low voltage level shifters, an ultra-low voltage level shifter was created. A physical prototype was implemented and manufactured in 130 nm bulk CMOS to demonstrate the principle. The assist circuit of the level shifter ensures a propagation delay of 21.08 ns, which results in an energy-efficient level shifter consuming 25.9 fJ per conversion when up-converting near-threshold input signals of 300 mV to regular supply voltage signals of 1.2V. Measurement results on ten samples show that the level shifter support up-conversion of logic signals with mean value down to 31.1 mV. By tuning the balance between the pullup and pull-down networks the mean value of the lower limit is decreased to 14.3 mV. Macro-level schemes have been considered to reduce the power consumption of already voltage scaled low voltage memories. Low voltage memory cells are typically asymmetric in nature, which leads to state-dependent pros and cons. We have introduced a scheme that dynamically exploits content-dependencies in asymmetric memory cells where words are conditionally flipped during write operations to reach the more beneficial state for storage. A capacitive logic decision circuit is created to perform the word-flip operation, and the system is exemplified with a 1 kb static random access memory macro of asymmetric low voltage memory cells that have a state-dependent leakage quotient of 23. The memory array and the scheme was implemented and manufactured in a 130 nm bulk process. Measurement results, on a physical prototype of the exemplified memory macro, with the scheme activated, show an improvement of 11.93% in retention power consumption when storing 128 words concatenated from random bits that are uniformly distributed. By applying voltage scaling on CMOS circuits, we have gained further insight into circuit architectures and schemes that ensures ressilient and robust operation while yielding energy efficiency and low power consumption. The results of this work are identifications of promising circuit architectures as well as the introduction of new schematics and approaches to the design of low voltage memories and logic cells.

• Aunet, Snorre; Ytterdal, Trond; Lande, Tor Sverre & Moulin, Kaspar Sigurd (2021). Low-Power Neuromorphic Sound Source Localization. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  I denne hovedoppgaven presenterer vi et neuromorft system for lydkildelokalisering basert på Jeffress sin lokaliseringsmodell. Systemet bruker nevral spike-koding og asynkrone delay-linjer for a beregne krysskorrelasjonen i tidsdomenet og bestemme tidsforsinkelsen mellom binaurale inngangssignaler. Vår tilnærming kan potensielt gi bedre ytelse enn dagens lokaliseringssystemer, med hensyn til effektforbruk og responstid. I de simulerte testene kan systemet estimere tidsforsinkelsen med omtrent 10us nøyaktighet, med et gjennomsnittlig effektforbruk på 350nW. Simuleringene viser også at systemet kan reagere på forandringer i tidsforsinkelsen på under et millisekund. Systemet er derimot svært avhengig av nøyaktig komponentmatching, og vil derfor kreve ytterligere former for kalibrering før fysisk implementering er mulig.

• Fosse, Carl Richard Steen; Tjora, Sigve & Aunet, Snorre (2020). Power consumption in relation to communication protocols used by a Nrf9160. Norges Teknisk Naturvitenskapelige Universitet. Full text in Research Archive
• Møklegård, Benjamin Ramberg & Aunet, Snorre (2020). AI on device Visual Occupancy Detection. Norges Teknisk Naturvitenskapelige Universitet. Full text in Research Archive
• Schoepe, Felix Allan; Reichelt, Pål Øyvind Gamst & Aunet, Snorre (2020). Ultra-low power accurate temperature sensor for IoT. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  The analog front-end of a proposed BJT-based temperature sensor has been designed. The design has been analysed using Monte-Carlo simulations with mismatch over all process corners. The design was implemented in a 90nm generic process design kit. The analog front-end achieves ultra-low power consumption with a current consumption of 2.3 mA at a temperature of 27 °C and can operate over the military temperature range of -55 °C - 125 °C. It uses a voltage supply of 2 V. An adaptive self-biasing operational amplifier was implemented in the bandgap reference circuit to ensure sufficiently high DC loop-gain. It operates on an ultra-low current consumption of 631 nA. To reduce errors due to mismatch and process spread two correction techniques have been employed, that is chopping of the input signals of the operational amplifier and dynamic element matching of the current sources in the bipolar core. The residual temperature reading error at the output of the analog front-end is large and results in significant errors. This is because no compensation technique was implemented in the analog front-end to compensate for process spread of the BJTs and should be implemented digitally. The temperature reading errors due to offset and mismatch in the current sources have been reduced to around 0.03 °C at a temperature of 27 °C. The noise in the circuit was analysed without the dynamic effects of the DEM because of its simple implementation and results in an equivalent temperature error of around 0.12 °C, which indicates the resolution that is achievable. The settling time of the circuit is in the range of 110 ms.

• Dieset, Herman Kristian; Qadir, Omer & Aunet, Snorre (2020). Approximate Arithmetical Operators for Energy Efficient Inference in Deep Neural Networks. NTNU. Full text in Research Archive Show summary

• Gausdal, Kaja; Gonsholt, Kyrre Erlend; Qadir, Omer & Aunet, Snorre (2020). Applying Asynchronous Completion Detection to the AVS Domain. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive
• Bygland, Embla Trasti; Austbø, Knut & Aunet, Snorre (2020). Power Modeling of Complex Designs. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  I dette prosjektet implementeres et verktøy for å lage effektmodeller av RTL design. Den genererte effektmodellen er ment å brukes sammen med et effektestimeringsverktøy for å gi et tidlig, raskt og nøyaktig effektestimat. Nordic Semiconductor ASA utsteder dette masterprosjektet med motivasjonen å gjøre RTL simuleringer effektbevisste. Å oppdage power bugs tidlig i implementeringen av en design kan spare iterasjoner i ASIC designflyten, og dermed redusere tiden som kreves for å få et produkt på markedet. Metoden for å estimere effekt på RTL kalt top-down metoden ble valgt for implementerin- gen. Blant andre ønskede kvaliteter krever det ikke en syntetisert nettliste-representasjon av designet for å produsere et effektestimat. Dette gjør at effektestimering kan gjøres samtidig med simuleringer for funksjonell verifisering av RTL, før syntesen av designet. Effektmodelleringen er delt inn i tre deler: 1. Hente ut strukturell informasjon fra en prosessert SystemVerilog representasjon av designet. 2. Hente ut informasjon om tilgjengelige celler og deres effektforbruk fra cellebiblioteket. 3. Kombinere den strukturelle representasjonen med celle- og effektinformasjonen, og lage en effektmodell. I implementasjonen er strukturen til et design representert av et nodetre, mens et cellebib- liotekobjekt er laget for å representere tilgjengelige celler fra cellebiblioteket og effektfor- bruket deres. For å produsere en effektmodell tar implementasjonen sekvenser av gener- iske celler fra strukturtreet og erstatter dem med celler hentet fra cellebiblioteket. Effekt- modellen består av flere effektbevisste nodetrær. Den effekt-bevisste representasjonen har mange likheter med den syntetiserte nettlisten. Dog, mer arbeid er nødvendig for å lage en god sammenligning mellom representasjonene. Implementasjonen er lovende for nøyaktig og rask høy-nivås estimering av effektforbruk. Flere abstraksjoner blir gjort i prosessen slik at estimasjonen er rask. Hvordan abstrak- sjonene påvirker effektestimatet er evaluert sammen med andre alternativer. Når et effekt- bevisst nodetre lages, grupperes generiske celler til mer komplekse celler fra cellebiblioteket. v Denne grupperingen gjør at antall celler i representasjonen reduseres, noe som bringer mod- ellen nærmere den syntetiserte nettlisten. Noe arbeid gjenstår for å gjøre effektmodellen komplett; flere komplekse generiske cel- lene fra den prosesserte SystemVerilog-filen må settes sammen av tilgjengelige celler fra cellebiblioteket. Komplekse generiske celler som ennå ikke har noen ekvivalent effektbevisst representasjon er de som representerer aritmetiske operasjoner, skiftere og komparatorer. Når disse generiske cellene har en representasjon i effektmodellen, kan signaler propageres gjennom strukturtrærne, og et effektestimat lages for hvert nodetre. Jobben til effektes- timeringsverktøyet som skal bruke effektmodellen er å kombinere aktivitetsdata fra en RTL- simulering med effektverdiene fra hvert nodetre i et vilkårlig design, og gi et effektestimat for designet.

• Vatanjou, Ali Asghar; Ytterdal, Trond & Aunet, Snorre (2019). Ultra Low-Power/Low-Energy CMOS Mixed-Signal Building Blocks. Norges teknisk-naturvitenskapelige universitet. ISSN 9788232643233. Full text in Research Archive Show summary

  In the present day microelectronics, supply voltage scaling has received an intense attention as an efficient approach to reduce the power consumption in battery-operated and energy-harvested wireless systems. However, process, voltage and temperature (PVT) variations increase with lowering the supply voltage. This poses a challenge to ultra-low voltage (ULV) design to make robust circuits while maintaining the energy efficiency. In this dissertation, ultra-low voltage building blocks are developed in 65 nm Bulk CMOS and 28 nm FDSOI technologies. The work focuses on making an optimal trade-off between the energy efficiency and the robustness of the building-blocks. At device level, combinations of higher order effects were considered. Static CMOS logic was used throughout the logic cells development. A constant effort was made to balance the drive strengths of the pull-up and pull-down networks with less area overhead and increase the functional yield of the cells. For the sequential elements, a single-phase clocked and contention free flip-flop structure was used. Measurement results confirmed robustness and energy efficiency of the circuits both in the 65 nm Bulk and 28 nm FDSOI technologies. In 65 nm, the obtained 119 mV and 84 mV minimum supply voltages for the Ripple Carry Adders (RCA) proved the robustness of two types of logic cells with thick and thin Gate-Oxide thicknesses. The functionality of the singlephase clocked D type flip-flops were proven down to 132 mV in a divide-by-3 circuit. In 28 nm FDSOI, a minimum functional supply voltage of 110 mV was achieved for RCAs and 8-bit multiplier based on Regular Threshold Voltage (RTV) devices. This is a demonstration of the functionality of both the combinational and sequential elements as the 8-bit multiplier contains the single-phased clocked flip-flops to sample outputs of the multiplier. Moreover, the minimum supply voltages of the 32-bit RCA samples reduced down to 80 mV by applying reverse back-gate voltages to the PMOS transistors. The 32-bit RCA based on minority-3 gates in 28 nm achieved an average energy per 1-bit addition of 0.65 fJ from the measurement results of nine samples. The average of measured energy per 1-bit addition of the 16-bit RCA was 0.77 fJ. From the measurements of ten samples, the implemented 8-bit multiplier in 28 nm obtained a minimum energy point of 47.2 fJ/cycle on average. The implemented logic cell library based on the Low Threshold Voltage (LVT) devices in 28 nm FDSOI was extended by adding specialized inverters for clock tree distribution and fixing the hold time violations. A simple approach for clock distribution is also presented when the sequential elements of the circuit are single-phase clocked and race free. A level-shifter capable of up-converting 39 mV to 1 V was implemented in 28 nm FDSOI. The diode connected devices were utilized to reduce the leakage current and decrease the minimum convertible input voltage levels. Moreover, the Single-NWELL (SNW) layout strategy was used along with the back-gate biasing and poly-biasing to create an adequate balance between the PMOS and NMOS drive strengths.

• Christensen, Steinar Thune; Aunet, Snorre & Qadir, Omer (2019). En Konfigurerbar og Fleksibel Arkitektur for Laveffekt, Energieffektiv Maskinvareakselerasjon av Nevrale Nettverk basert på Foldning. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Nevrale nettverk basert på foldning (CNNs) har blitt essensielle i dagens Kunstig-Intelligensog Maskinlærings-anvendelser. Dette gjelder særlig bildegjenkjenning. Denne masteroppgaven presenterer en konfigurerbar, allsidig og fleksibel arkitektur for maskinvareakselerasjon av CNNs som er basert på å lagre og akkumulere hele feature maps i lokalt minne inne i akseleratoren. Dette har blitt gjort med et mål om å være i stand til å prosessere enhver type CNN med så lavt effektforbruk og så høy energieffektivitet som mulig. Energieffektivitet viser til antall operasjoner per energienhet (målt i antall multiplikasjon-akkumulasjon-operasjoner per energienhet, MACs/s/W eller MACs/J). Flere ulike utgaver av arkitekturen har blitt syntetisert og testet med ulike konfigurasjoner. Sammenliknet med dagens beste akseleratorer preseterer den godt, den oppnår en energieffektivitetøkning med faktor større enn 5 for utvalgte CNN-lag. Den mest energieffektive konfigurasjonen oppnår 175 MACs/s/W med et effektforbruk på 2.3 mW og et arealforbruk på 585 KGEs (Kilo Gate Equivalents) med 1V forsyningsspenning og en klokkefrekvens på 100 MHz. Dette er en betydelig forbedring over Eyeriss [YuH17b] (en av dagens beste akseleratorer) som har en maksimal energieffektivitet på 122.8 MACs/s/W.

• Paintsil, Wesley Ryan; Aunet, Snorre & Moldsvor, Øystein (2019). A comparative study for commercial TVOC sensors. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Indoor air quality has become more important as human activity is increasingly spent inside. Internet of things has allowed for humans to better interact with the physical world by extracting information through sensor nodes. Indoor air quality sensors of different types have become increasingly popular, this thesis focuses on total volatile organic compound sensors. Three different sensors have been chosen and their operations evaluated by their power consumption. The Bosch BME680 proved to be the best sensor in terms of low-power, it had a lifetime of 4847 days as an alarm system and a lifetime of 2403 days if it acted as a monitoring system. The Integrated Devices Technologies ZMOD4410 only had a lifetime of 8 days. The AMS CCS811 had a lifetime of 871 days as an alarm system and 191 as a monitoring system. The BME680 had an integrated humidity and temperature sensor which provided an advantage by letting the host controller sleep longer. It should be possible to drive the BME680 and the CCS811 sensor with a 230mAh battery for more than 2 years.

• Boland, Connor; Aunet, Snorre & Moldsvor, Øystein (2019). Low Power Environmental Air Quality Monitoring. Norges teknisk-naturvitenskapelige universitet. Full text in Research Archive Show summary

  Måling av personlig miljøluftkvalitet blir stadig mer relevant i dagens samfunn. Tradisjonell overvåking krever overdimensjonerte, dyre instrumenter, med langsomme og intensive prøvetakingsmetoder. Skalerbare, lavprismonitorer kreves for å erstatte disse utdaterte designene, for dermed å øke global tilgang til luftkvalitetsdata. Disruptive Technologies designer og produserer IoT-løsninger og spesialiserer seg på smarte trådløse sensorer med lang batterilevetid. Målet med dette prosjektet er derfor å utvikle en batteridrevet miljøkvalitetsmonitor, med tilsvarende batterilevetid som Disruptive Technologies eksisterende sensorer. Monitoren må ikke bare kunne måle et antall skadelige luftforurensninger, men også vurdere arbeidsmiljø. Det legges spesiell vekt på partikkeldeteksjon da det vil gi monitoren kommersiell levedyktighet. En rekke partikkelsensorer ble introdusert. Innledende målinger på hver sensor ble utført for å teste deres egnethet som en del av en komplett batteridrevet skjerm. Av alle de testede sensorene viste bare Sharp GP2Y10AU0F, en kompakt optisk støvsensor, lavt nok strømtrekk for batteridrift. En rekke teknikker for å redusere strømtrekket ble introdusert som en del av et testdesign med Sharp-sensoren og en mikrokontroller. Det totale beregnede energibehovet til sensoren kom på 1 638J for to års levetid. Sharp-sensoren ble kombinert med to andre sensorer (en sensor som måler både flyktige organiske kjemikalier (VOC) og karbondioksid (CO2) og en sensor måler temperatur og luftfuktighet) som en modell for de komplette energibehovene til monitoren . Det totale beregnede strømforbruket kom til 125 968J, som langt overstiger en standard batterikapasitet på opptil 39 960J. Den uforutsette energibegrensningen til dette designet var med den valgte VOC sensoren, men prosjektet har fortsatt vist mulige muligheter for en batteridrevet miljøkvalitetsmonitor som er i stand til å måle luftpartikler.

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