The network on chip is an integral part of modern multicore systems. To allow for scalability to hundreds of cores it is important that the switches in the on-chip network are flexible without consuming too much of the chip resources. To this effect, most on chip routing mechanisms rely on logic-based decisions. These pose significant challenges in terms of reconfigurability and routing efficiency.
The candidate will study existing logic-based routing implementations in an attempt to understand and characterised the relationship between the functionality and complexity of the mechanisms. This information may be used to develop new routing concepts for networks on chip. The work will rely heavily on simulations.
For more information, please contact Frank Olaf Sem-Jacobsen (frankose@simula.no)