1. Title: "MiniMINC ASIC for thermal image sensor". The goal is to design a micro-bolometer array readout ASIC (the MiniMINC) based on the existing IDEAS MINC circuit. The MiniMINC shall interface to existing NIRCA MkII. The work will start with from the existing MINC design database, remove unwanted parts of the circuit, transfer the remaining design to 180nm CMOS in TMSC/AMS/XFAB (tbd), add an analog output buffer, prepare layout, verification, up to tapeout to the foundry. All IP remains with IDEAS. Advisor: one of Hans/Amir/Joerg
2. Title: "3DMUSE at IDEAS". ASIC design work in 28nm FDSOI CMOS, and experimental work on TDC characterization. Start with existing TDC design and design an input stage for interfacing to external SiPM. Design in 28nm STM FDSOI CMOS. At the same time test an existing TDC from first fabrication in the IDEAS lab. Advisor: Joar
3. Title: "Low-power and high-rate single photon counting ASIC". The goal is to design a low-power and high-rate readout for SiPM arrays. Start from the existing IDEAS APOCAT ASIC analog channel and remove current mode input stage and the CSA. Instead add a passive current integrator (capacitor and resistors) with digital and staged reset. This has the benefit of removing the relatively high-power input stages, and the disadvantage of increasing the noise. The latter is acceptable in for certain applications. The work includes some characterization of the existing APOCAT ASIC, and new design work along the roadmap for low-power and high-rate single photon counting. Advisor: Joar