Mixed-signal 3D integrated circuit architectures
This is a collection of projects contributing the EU research project 3D-MUSE. 3D-MUSE develops 3D integrated circuit technology, where transistors are not only implemented on a 2D chip but can be stacked on top of each other, allowing for extremely dense integrated circuits. Specifically, 3D-MUSE aims at 100 times higher density of vertical connections than the current state of the art. This allows completely new concepts of 3D circuit architectures, particularly for mixed signal circuits. Multiple MSc projects in this domain shall systematically and quantitatively compare 2D circuit designs with 3D designs and analyse possible benefits and drawbacks.
Cross section of two transistors on top of eachother in sequential 3D CMOS (curtesy of 3D-MUSE partner CEA/LETI)
One obvious benefit from going to very dense 3D circuit architectures comes from reduced interconnect density: the total length of connections between circuit elements can be much reduced whan going from 2D to 3D. Thereby, parasitic capacitance is reduced and energy consumption for transmitting signals is automatically reduced.
Slightly less obvious benefits are noise performance as well as options for massive parallelization when processing signals from sensor arrays.
Candidate circuit architectures to look into can be smart image sensors and other 2D sensor arrays, in general ADC and DAC architectures, neural network circuits etc. There will be several MSc projects in this domain. Come and discuss your own option with me!
To execute the projects we do have 3D design tools from the 3D-MUSE projects in sequential 3D 28nm FDSOI CMOS technology. Required skills are thus some familiarity with the Cadence circuit layout editing tool as introduced in IN5180, INF4420 and some basic familiarity with CMOS circuit design as introduced in /N3170/4170, INF3410.