Softcore HDL processor for implementation on ASIC
The development of integrated circuit technologies makes it possible to integrate complete systems on one chip consisting of microprocessors, RAM, dedicated digital modules as well as analogue elements like sensor front-ends, RF modules and power regulators, image pixels, MEMS-structures (pressure sensors, mechanical switches, accelerometers), high quality coils and capacitors etc. This is known as System on Chip (SoC). Development of a SoC is done in several steps where the different modules are developed and verified in different devices before they may be combined into one circuit.
The Nanoelectronics group at IFI develop ASICs for application areas like medical, space, biology, health and high quality measurements. In many cases it would be attractive to have a small general processor that may be implemented on our ASICs together with the other circuitry we develop. We would like to have a processor core that is described in an HDL-language and that can be synthesised both on FPGAs and on an ASIC. It is important that it can be implemented in both and have same/similar functionality in both. An FPGA implementation is important to simplify development and verification of the digital structure but also because in many cases an FPGA implementation is sufficient together with an analogue ASIC. In other cases, the FPGA implementation is only for functional verification before the HDL description is ported to ASIC technologies supporting higher voltages, higher or lower temperatures, harder radiation or lower power consumption than what standard (FPGA) technologies are able to manage. Today there are a number of soft core processors available free or for a low cost. However, their support for software (C-compilers etc.) is very variable.
The project has already undergone a number of iterations. A first part has been to get an overview over promising software cores, their functionality, performance and support. Also soft core processors (with RAM etc.) on an FPGA have been implemented and their functionality and performance have been analyzed. Right now it looks to us that the RISC-V processors are the most interesting option, with a number of cores and their VHDL code available as open source. So it is now is the goal that the structure should be synthesised on an ASIC .
The master work will be related to the 4Dspace activity as a target application but inputs from other projects would also be beneficial.
An interested student must have (or take) relevant courses in VHDL (or similar) languages. He/she should also have some competence or interest in processor architectures. It is an advantage if the student has competence/interest in digital signal processing, RF, PCB design or ASIC design but this is not a requirement.
It is possible that two students may cooperate on this task.