VCO-based column-ADCs for CMOS image sensors

CMOS image sensors (CIS) are widely adopted in many application fields, such as industry control system, automotive, consumer electronics, surveillance system, and so on. Inside of a CIS, a column-ADC based readout architecture is commonly employed because of its high-speed and low-noise readout capability. To improve readout speed and noise performance of column-parallel readout architecture, a compact and efficient column ADC structure is desired. A VCO-based voltage-to-frequency or voltage-to-digital converter is a promising candidate for real column level ADC that could be contained completely inside of column array.

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This is a project in collaboration with SONY Semiconductor Solutions Europe

This project is going to explore the possibility to implement a VCO-based ADC with challenging design constraints; including narrow column pitch of layout area (width less than 1.5 um), limited total column layout area (height less than 1000 um), low power supply (0.8 V), low power consumption (limited current supply), lower cross-talk between columns, high operation frequency/readout speed, low readout noise. The expected goal of this project is to provide a better column-parallel readout architecture than existing SS ADCs with lower power consumption, smaller area, higher readout speed, and lower readout noise.

The student who would like to work on this challenging design is expected to have good understanding about both analogue and digital IC design. To be able to investigate VCO-based ADC structure based on published technical/academy papers, analyse, evaluate and conclude if it is possible to implement a VCO-based ADC at column-level. The student should also be able to design and implement VCO-based ADC in a column array.

Emneord: ASIC, CMOS, Image Sensor, ADC, VCO
Publisert 26. okt. 2020 13:56 - Sist endret 27. okt. 2020 10:41

Omfang (studiepoeng)